diff options
| author | Prashanth Mundkur | 2018-11-21 14:02:18 -0800 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-11-21 14:19:21 -0800 |
| commit | 01a6e9b8ad00728fdbf12a76cda24144a75ec552 (patch) | |
| tree | 2026fcadd803d41fb1aac4a8de7f4b1a71a94c07 /riscv/riscv_sim.c | |
| parent | b5cdd319822f9b2836a3bccf827121cb7ab0a105 (diff) | |
RISC-V: allow platform ram size to be configurable.
Diffstat (limited to 'riscv/riscv_sim.c')
| -rw-r--r-- | riscv/riscv_sim.c | 26 |
1 files changed, 21 insertions, 5 deletions
diff --git a/riscv/riscv_sim.c b/riscv/riscv_sim.c index 06f9bd66..394277a7 100644 --- a/riscv/riscv_sim.c +++ b/riscv/riscv_sim.c @@ -52,6 +52,7 @@ size_t spike_dtb_len = 0; static struct option options[] = { {"enable-dirty", no_argument, 0, 'd'}, {"enable-misaligned", no_argument, 0, 'm'}, + {"ram-size", required_argument, 0, 'z'}, {"mtval-has-illegal-inst-bits", no_argument, 0, 'i'}, {"dump-dts", no_argument, 0, 's'}, {"device-tree-blob", required_argument, 0, 'b'}, @@ -75,7 +76,7 @@ static void dump_dts(void) { #ifdef SPIKE size_t dts_len = 0; - struct tv_spike_t *s = tv_init("RV64IMAC", 0); + struct tv_spike_t *s = tv_init("RV64IMAC", rv_ram_size, 0); tv_get_dts(s, NULL, &dts_len); if (dts_len > 0) { unsigned char *dts = (unsigned char *)malloc(dts_len + 1); @@ -122,14 +123,17 @@ static void read_dtb(const char *path) char *process_args(int argc, char **argv) { int c, idx = 1; + uint64_t ram_size = 0; while(true) { - c = getopt_long(argc, argv, "dmsb:t:v:h", options, &idx); + c = getopt_long(argc, argv, "dmsz:b:t:v:h", options, &idx); if (c == -1) break; switch (c) { case 'd': + fprintf(stderr, "enabling dirty update.\n"); rv_enable_dirty_update = true; break; case 'm': + fprintf(stderr, "enabling misaligned access.\n"); rv_enable_misaligned = true; break; case 'i': @@ -137,6 +141,13 @@ char *process_args(int argc, char **argv) case 's': do_dump_dts = true; break; + case 'z': + ram_size = atol(optarg); + if (ram_size) { + fprintf(stderr, "setting ram-size to %ld MB\n", ram_size); + rv_ram_size = ram_size << 20; + } + break; case 'b': dtb_file = strdup(optarg); break; @@ -179,11 +190,11 @@ uint64_t load_sail(char *f) return entry; } -void init_spike(const char *f, uint64_t entry) +void init_spike(const char *f, uint64_t entry, uint64_t ram_size) { #ifdef SPIKE bool mismatch = false; - s = tv_init("RV64IMAC", 1); + s = tv_init("RV64IMAC", ram_size, 1); if (tv_is_dirty_enabled(s) != rv_enable_dirty_update) { mismatch = true; fprintf(stderr, "inconsistent enable-dirty-update setting: spike %s, sail %s\n", @@ -196,6 +207,11 @@ void init_spike(const char *f, uint64_t entry) tv_is_misaligned_enabled(s) ? "on" : "off", rv_enable_misaligned ? "on" : "off"); } + if (tv_ram_size(s) != rv_ram_size) { + mismatch = true; + fprintf(stderr, "inconsistent ram-size setting: spike %lx, sail %lx\n", + tv_ram_size(s), rv_ram_size); + } if (mismatch) exit(1); /* The initialization order below matters. */ @@ -491,7 +507,7 @@ int main(int argc, char **argv) /* initialize spike before sail so that we can access the device-tree blob, * until we roll our own. */ - init_spike(file, entry); + init_spike(file, entry, rv_ram_size); init_sail(entry); if (!init_check(s)) finish(1); |
