diff options
| author | Prashanth Mundkur | 2018-06-25 12:39:42 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-06-25 15:36:08 -0700 |
| commit | c091410169c5ead5c39fa72d80fb52e22cd0d3dd (patch) | |
| tree | ad688aa4b21d9912352ca565f7c5eb7868450906 /riscv/riscv_platform.sail | |
| parent | 71637ed07d4df310b6e9a10419d2ce0375d1de30 (diff) | |
Fix riscv interrupt pending check to handle implicit enabling at lower privileges.
Also fix timer threshold comparison to be <= instead of <.
Diffstat (limited to 'riscv/riscv_platform.sail')
| -rw-r--r-- | riscv/riscv_platform.sail | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/riscv/riscv_platform.sail b/riscv/riscv_platform.sail index 55df7c5c..bfeff01d 100644 --- a/riscv/riscv_platform.sail +++ b/riscv/riscv_platform.sail @@ -105,12 +105,10 @@ function clint_load(addr, width) = { function clint_dispatch() -> unit = { print("clint::tick mtime <- " ^ BitStr(mtime)); mip->MTI() = false; - if mtimecmp <_u mtime & mtimecmp != EXTZ(0b0) then { - print(" firing clint timer at mtime " ^ BitStr(mtime)); + if mtimecmp <=_u mtime then { + print(" clint timer pending at mtime " ^ BitStr(mtime)); mip->MTI() = true - }; - if mtimecmp != EXTZ(0b0) & mtimecmp != EXTS(0b1) then - print(" mtime=" ^ BitStr(mtime) ^ " mtimecmp=" ^ BitStr(mtimecmp)); + } } /* The rreg effect is due to checking mtime. */ |