diff options
| author | Thomas Bauereiss | 2018-06-07 13:58:49 +0100 |
|---|---|---|
| committer | Thomas Bauereiss | 2018-06-07 14:04:48 +0100 |
| commit | 92a158886dd4fa2b5fed6bb9db29c7307a4d07d4 (patch) | |
| tree | e7e07e1f8c05f3918e954b4c71025af54185805c /riscv/riscv_platform.sail | |
| parent | 27a88d181e8d01b042730b2aac7e19867aa10548 (diff) | |
Fix Lem build of RISC-V
Diffstat (limited to 'riscv/riscv_platform.sail')
| -rw-r--r-- | riscv/riscv_platform.sail | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/riscv_platform.sail b/riscv/riscv_platform.sail index 8f4e923a..f3911ba9 100644 --- a/riscv/riscv_platform.sail +++ b/riscv/riscv_platform.sail @@ -53,9 +53,9 @@ function clint_load(addr, width) = { if addr == MSIP_BASE & ('n == 8 | 'n == 4) then MemValue(zero_extend(mip.MSI(), sizeof(8 * 'n))) else if addr == MTIMECMP_BASE & ('n == 8) - then MemValue(mtimecmp) + then MemValue(zero_extend(mtimecmp, 64)) /* FIXME: Redundant zero_extend currently required by Lem backend */ else if addr == MTIME_BASE & ('n == 8) - then MemValue(mtime) + then MemValue(zero_extend(mtime, 64)) else MemException(E_Load_Access_Fault) } @@ -65,7 +65,7 @@ function clint_store(addr, width, data) = { mip->MSI() = data[0] == 0b1; MemValue(()) } else if addr == MTIMECMP_BASE & 'n == 8 then { - mtimecmp = data; + mtimecmp = zero_extend(data, 64); /* FIXME: Redundant zero_extend currently required by Lem backend */ MemValue(()) } else MemException(E_SAMO_Access_Fault) } |
