diff options
| author | Prashanth Mundkur | 2018-06-22 17:14:35 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-06-22 17:46:59 -0700 |
| commit | 74e459da59e8411de84bded89d010e62fd735d29 (patch) | |
| tree | 22a40cd953b990973efb6795434602df2571f9b4 /riscv/riscv_platform.sail | |
| parent | 66ae0071f94a1ee33b021a5a0d34acbd510a8827 (diff) | |
Make riscv pte dirty-bit update handling configurable via a platform cli option.
Fix a redundant clock tick.
Diffstat (limited to 'riscv/riscv_platform.sail')
| -rw-r--r-- | riscv/riscv_platform.sail | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/riscv_platform.sail b/riscv/riscv_platform.sail index c6786ff7..27c774cc 100644 --- a/riscv/riscv_platform.sail +++ b/riscv/riscv_platform.sail @@ -10,6 +10,9 @@ val plat_ram_base = {ocaml: "Platform.dram_base", lem: "plat_ram_base"} : unit -> xlenbits val plat_ram_size = {ocaml: "Platform.dram_size", lem: "plat_ram_size"} : unit -> xlenbits +/* whether the MMU should update dirty bits in PTEs */ +val plat_enable_dirty_update = {ocaml: "Platform.enable_dirty_update", lem: "plat_enable_dirty_update"} : unit -> bool + /* ROM holding reset vector and device-tree DTB */ val plat_rom_base = {ocaml: "Platform.rom_base", lem: "plat_rom_base"} : unit -> xlenbits val plat_rom_size = {ocaml: "Platform.rom_size", lem: "plat_rom_size"} : unit -> xlenbits |