diff options
| author | Prashanth Mundkur | 2018-06-25 16:08:39 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-06-25 16:08:39 -0700 |
| commit | 090d2b38c09f12fdbb677b94b94ac7d86bb8c789 (patch) | |
| tree | 7810094cb91b527bd83540ab74eef36f86d6f45f /riscv/riscv_platform.sail | |
| parent | 768728bc21bb45b39494443f81f3e9de65f94fe1 (diff) | |
Add a riscv platform parameter to control trapping to M-mode on misaligned access, and a cli option to control it.
Diffstat (limited to 'riscv/riscv_platform.sail')
| -rw-r--r-- | riscv/riscv_platform.sail | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/riscv/riscv_platform.sail b/riscv/riscv_platform.sail index bfeff01d..bf0e5020 100644 --- a/riscv/riscv_platform.sail +++ b/riscv/riscv_platform.sail @@ -11,7 +11,14 @@ val plat_ram_base = {ocaml: "Platform.dram_base", lem: "plat_ram_base"} : unit - val plat_ram_size = {ocaml: "Platform.dram_size", lem: "plat_ram_size"} : unit -> xlenbits /* whether the MMU should update dirty bits in PTEs */ -val plat_enable_dirty_update = {ocaml: "Platform.enable_dirty_update", lem: "plat_enable_dirty_update"} : unit -> bool +val plat_enable_dirty_update = {ocaml: "Platform.enable_dirty_update", + lem: "plat_enable_dirty_update"} : unit -> bool + +/* whether the platform supports misaligned accesses without trapping to M-mode. if false, + * misaligned loads/stores are trapped to Machine mode. + */ +val plat_enable_misaligned_access = {ocaml: "Platform.enable_misaligned_access", + lem: "plat_enable_misaligned_access"} : unit -> bool /* ROM holding reset vector and device-tree DTB */ val plat_rom_base = {ocaml: "Platform.rom_base", lem: "plat_rom_base"} : unit -> xlenbits |