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authorThomas Bauereiss2018-03-14 10:56:57 +0000
committerThomas Bauereiss2018-03-14 12:21:47 +0000
commit71febd33cb9759ee524b6d7a8be3b66cba236c0e (patch)
tree28f3e704cce279bd209d147a0a4e5dee82cbe75a /riscv/riscv_extras.lem
parentbe1f5f26ca68fad23eada8a3adb5cfb6b958ff51 (diff)
Make partiality more explicit in library functions of Lem shallow embedding
Some functions are partial, e.g. converting a bitvector to an integer, which might fail for the bit list representation due to undefined bits. Undefined cases can be handled in different ways: - call Lem's failwith, which maps to undefined/ARB in Isabelle and HOL (the default so far), - return an option type, - raise a failure in the monad, or - use a bitstream oracle to resolve undefined bits. This patch adds different versions of partial functions corresponding to those options. The desired behaviour can be selected by choosing a binding in the Sail prelude. The naming scheme is that the failwith version is the default, while the other versions have the suffixes _maybe, _fail, and _oracle, respectively.
Diffstat (limited to 'riscv/riscv_extras.lem')
-rw-r--r--riscv/riscv_extras.lem6
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/riscv_extras.lem b/riscv/riscv_extras.lem
index 49499445..9d9ccf89 100644
--- a/riscv/riscv_extras.lem
+++ b/riscv/riscv_extras.lem
@@ -49,7 +49,7 @@ let get_slice_int len n lo =
(* TODO: Is this the intended behaviour? *)
let hi = lo + len - 1 in
let bits = bits_of_int (hi + 1) n in
- of_bits (get_bits false bits hi lo)
+ of_bits_failwith (subrange_list false bits hi lo)
val sign_extend : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> integer -> bitvector 'b
let sign_extend v len = exts_vec len v
@@ -57,9 +57,9 @@ val zero_extend : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> integer -> b
let zero_extend v len = extz_vec len v
val shift_bits_right : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a
-let shift_bits_right v m = shiftr v (unsigned m)
+let shift_bits_right v m = shiftr v (uint m)
val shift_bits_left : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a
-let shift_bits_left v m = shiftl v (unsigned m)
+let shift_bits_left v m = shiftl v (uint m)
val prerr_endline : string -> unit
let prerr_endline _ = ()