diff options
| author | Prashanth Mundkur | 2018-06-08 16:33:03 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-06-08 16:33:03 -0700 |
| commit | 33070c39f713041c6ba5e8ba2c9149b91c53f027 (patch) | |
| tree | 4a6c3023200dbe5f782651ca0ea818497e85bac5 /riscv/riscv.sail | |
| parent | d71ba6318512ffe7cd5221f20c405a38086e41e5 (diff) | |
Add counteren registers.
Diffstat (limited to 'riscv/riscv.sail')
| -rw-r--r-- | riscv/riscv.sail | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail index e855a53d..91af45cf 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -829,6 +829,7 @@ function readCSR csr : csreg -> xlenbits = 0x303 => mideleg.bits(), 0x304 => mie.bits(), 0x305 => mtvec.bits(), + 0x306 => EXTS(mcounteren.bits()), 0x340 => mscratch, 0x341 => mepc, 0x342 => mcause.bits(), @@ -841,6 +842,7 @@ function readCSR csr : csreg -> xlenbits = 0x103 => sideleg.bits(), 0x104 => lower_mie(mie, mideleg).bits(), 0x105 => stvec.bits(), + 0x106 => EXTS(scounteren.bits()), 0x140 => sscratch, 0x141 => sepc, 0x142 => scause.bits(), @@ -869,6 +871,7 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = 0x303 => { mideleg = legalize_mideleg(mideleg, value); Some(mideleg.bits()) }, 0x304 => { mie = legalize_mie(mie, value); Some(mie.bits()) }, 0x305 => { mtvec = legalize_tvec(mtvec, value); Some(mtvec.bits()) }, + 0x306 => { mcounteren = legalize_mcounteren(mcounteren, value); Some(EXTS(mcounteren.bits())) }, 0x340 => { mscratch = value; Some(mscratch) }, 0x341 => { mepc = legalize_xepc(value); Some(mepc) }, 0x342 => { mcause->bits() = value; Some(mcause.bits()) }, @@ -881,6 +884,7 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = 0x103 => { sideleg->bits() = value; Some(sideleg.bits()) }, /* TODO: does this need legalization? */ 0x104 => { mie = legalize_sie(mie, mideleg, value); Some(mie.bits()) }, 0x105 => { stvec = legalize_tvec(stvec, value); Some(stvec.bits()) }, + 0x106 => { scounteren = legalize_scounteren(scounteren, value); Some(EXTS(scounteren.bits())) }, 0x140 => { sscratch = value; Some(sscratch) }, 0x141 => { sepc = legalize_xepc(value); Some(sepc) }, 0x142 => { scause->bits() = value; Some(scause.bits()) }, |