diff options
| author | Prashanth Mundkur | 2018-07-09 00:15:20 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-07-09 00:15:20 -0700 |
| commit | 2c1dfb042ecc10c0ca7868ab186ff8235926d8d3 (patch) | |
| tree | a98714104f35ba1037c12e59ba93cdb69b2fc7f4 /riscv/riscv.sail | |
| parent | b9d6151e8671a03eb58f2065e85367fff0a27cf0 (diff) | |
Support writes to misa.C in riscv.
Diffstat (limited to 'riscv/riscv.sail')
| -rw-r--r-- | riscv/riscv.sail | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail index 0b651f04..7ba02a77 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -1159,7 +1159,7 @@ function readCSR csr : csreg -> xlenbits = 0x305 => mtvec.bits(), 0x306 => EXTZ(mcounteren.bits()), 0x340 => mscratch, - 0x341 => mepc, + 0x341 => mepc & pc_alignment_mask(), 0x342 => mcause.bits(), 0x343 => mtval, 0x344 => mip.bits(), @@ -1175,7 +1175,7 @@ function readCSR csr : csreg -> xlenbits = 0x105 => stvec.bits(), 0x106 => EXTZ(scounteren.bits()), 0x140 => sscratch, - 0x141 => sepc, + 0x141 => sepc & pc_alignment_mask(), 0x142 => scause.bits(), 0x143 => stval, 0x144 => lower_mip(mip, mideleg).bits(), |