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| author | Prashanth Mundkur | 2018-05-02 11:42:57 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-05-02 11:42:57 -0700 |
| commit | f439a12639b23ffbf86c440431b632019d298d7f (patch) | |
| tree | 08881f74f89b34d05ceaccbcc71f7d8e66331058 /riscv/main.sail | |
| parent | 47b02bcbf94c24f258cb7d5c67c11d020352b34c (diff) | |
Tick cycle counter in execute loop.
Diffstat (limited to 'riscv/main.sail')
| -rw-r--r-- | riscv/main.sail | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/main.sail b/riscv/main.sail index b6484755..80a637a0 100644 --- a/riscv/main.sail +++ b/riscv/main.sail @@ -8,6 +8,7 @@ val elf_tohost = { function fetch_and_execute () = let tohost = __GetSlice_int(64, elf_tohost(), 0) in while true do { + tick_clock(); print_bits("\nPC: ", PC); /* for now, always fetch a 32-bit value. this would need to |