Initial support for faults of reads to physical addresses.

1 files changed, 36 insertions, 33 deletions

diff --git a/riscv/main.sail b/riscv/main.sail
index 66ac89bd..b6484755 100644
--- a/riscv/main.sail
+++ b/riscv/main.sail
@@ -13,32 +13,43 @@ function fetch_and_execute () =
     /* for now, always fetch a 32-bit value.  this would need to
        change with privileged mode, since we could cross a page
        boundary with PC only 16-bit aligned in C mode.  */
-    let instr = __RISCV_read(PC, 4);
-
-    let (instr_ast, instr_sz) : (option(ast), int)=
-       match (instr[1 .. 0]) {
-         0b11 => (decode(instr), 4),
-	 _    => (decodeCompressed(instr[15 .. 0]), 2)
-       };
-    match (instr_ast, instr_sz) {
-      (Some(ast), 4) => print(BitStr(instr)          ^ ":  " ^ ast),
-      (Some(ast), 2) => print(BitStr(instr[15 .. 0]) ^ ":  " ^ ast),
-      (_,         _) => print(BitStr(instr)          ^ ":  no-decode")
-    };
-    /* check whether a compressed instruction is legal. */
-    if (misa.C() == 0b0 & (instr_sz == 2)) then {
-      let t : sync_exception =
-      struct { trap = E_Illegal_Instr,
-               excinfo = Some (EXTZ(instr)) } in
-      nextPC = handle_exception_ctl(cur_privilege, CTL_TRAP(t), PC)
-    } else {
-      nextPC = PC + instr_sz;
-      match instr_ast {
-        Some(ast) => execute(ast),
-	None()    => {print("Decode failed"); exit()}
+    let irdval = checked_mem_read(Instruction, PC, 4);
+    match (irdval) {
+      MemValue(instr) => {
+        let (instr_ast, instr_sz) : (option(ast), int) =
+          match (instr[1 .. 0]) {
+             0b11 => { cur_inst = EXTZ(instr);
+                       (decode(instr), 4)
+                     },
+             _    => { cur_inst = EXTZ(instr[15 .. 0]);
+                       (decodeCompressed(instr[15 .. 0]), 2)
+                     }
+          };
+        match (instr_ast, instr_sz) {
+          (Some(ast), 4) => print(BitStr(instr)          ^ ":  " ^ ast),
+          (Some(ast), 2) => print(BitStr(instr[15 .. 0]) ^ ":  " ^ ast),
+          (_,         _) => print(BitStr(instr)          ^ ":  no-decode")
+        };
+        /* check whether a compressed instruction is legal. */
+        if (misa.C() == 0b0 & (instr_sz == 2)) then {
+          let t : sync_exception = struct { trap = E_Illegal_Instr,
+                                            excinfo = Some(cur_inst) } in
+          nextPC = handle_exception_ctl(cur_privilege, CTL_TRAP(t), PC)
+        } else {
+          nextPC = PC + instr_sz;
+          match instr_ast {
+            Some(ast) => execute(ast),
+            None()    => {print("Decode failed"); exit()}
+          }
+        }
+      },
+      MemException(e) => {
+        let t : sync_exception = struct { trap = e,
+                                          excinfo = Some(PC) } in
+        nextPC = handle_exception_ctl(cur_privilege, CTL_TRAP(t), PC)
       }
     };
-    let tohost_val = __RISCV_read(tohost, 4);
+    let tohost_val = __ReadRAM(64, 4, 0x0000_0000_0000_0000, tohost);
     if unsigned(tohost_val) != 0 then {
       let exit_val = unsigned(tohost_val >> 0b1) in
       if exit_val == 0 then
@@ -57,13 +68,6 @@ val elf_entry = {
 
 val main : unit -> unit effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg}
 
-function dump_state () : unit -> unit = {
-  print("Dumping state");
-  print_bits(" PC: ", PC);
-  let instr = __RISCV_read(PC, 4);
-  print_bits(" instr: ", instr)
-}
-
 function main () = {
   PC = __GetSlice_int(64, elf_entry(), 0);
   try {
@@ -74,6 +78,5 @@ function main () = {
     Error_misaligned_access() => print("Error: misaligned_access"),
     Error_EBREAK() => print("EBREAK"),
     Error_internal_error() => print("Error: internal error")
-  };
-  dump_state ()
+  }
 }