summaryrefslogtreecommitdiff
path: root/riscv/main.sail
diff options
context:
space:
mode:
authorPrashanth Mundkur2018-05-03 15:02:08 -0700
committerPrashanth Mundkur2018-05-03 15:02:08 -0700
commitc4af140507927c924065c5d32235f258b200a203 (patch)
tree8ae74895e7789666e582ea52b52791d6987a3b4c /riscv/main.sail
parente39941e0ddf924502d17dc55f94fe09f1e4494d0 (diff)
Fix up interrupt and exception dispatch.
Diffstat (limited to 'riscv/main.sail')
-rw-r--r--riscv/main.sail4
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/main.sail b/riscv/main.sail
index 80a637a0..6337826e 100644
--- a/riscv/main.sail
+++ b/riscv/main.sail
@@ -35,7 +35,7 @@ function fetch_and_execute () =
if (misa.C() == 0b0 & (instr_sz == 2)) then {
let t : sync_exception = struct { trap = E_Illegal_Instr,
excinfo = Some(cur_inst) } in
- nextPC = handle_exception_ctl(cur_privilege, CTL_TRAP(t), PC)
+ nextPC = handle_exception(cur_privilege, CTL_TRAP(t), PC)
} else {
nextPC = PC + instr_sz;
match instr_ast {
@@ -47,7 +47,7 @@ function fetch_and_execute () =
MemException(e) => {
let t : sync_exception = struct { trap = e,
excinfo = Some(PC) } in
- nextPC = handle_exception_ctl(cur_privilege, CTL_TRAP(t), PC)
+ nextPC = handle_exception(cur_privilege, CTL_TRAP(t), PC)
}
};
let tohost_val = __ReadRAM(64, 4, 0x0000_0000_0000_0000, tohost);