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authorPrashanth Mundkur2018-01-29 08:26:13 -0800
committerPrashanth Mundkur2018-01-29 08:26:50 -0800
commit62af7ede74637199eadac4bfe19d414caca66d48 (patch)
tree44f0d255411fa0a866f0329d4a2b33f81ac1664f /riscv/main.sail
parent8406a2ec3aeab4ad573a126adb3393e7033d749b (diff)
Add some initial exception handling to the riscv execution loop.
Diffstat (limited to 'riscv/main.sail')
-rw-r--r--riscv/main.sail17
1 files changed, 16 insertions, 1 deletions
diff --git a/riscv/main.sail b/riscv/main.sail
index 8c93afdc..cc6bb90c 100644
--- a/riscv/main.sail
+++ b/riscv/main.sail
@@ -29,7 +29,22 @@ val elf_entry = "Elf_loader.elf_entry" : unit -> int
val main : unit -> unit effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg}
+function dump_state () : unit -> unit = {
+ print("Dumping state");
+ print_bits(" PC: ", PC);
+ let instr = __RISCV_read(PC, 4);
+ print_bits(" instr: ", instr)
+}
+
function main () = {
PC = __GetSlice_int(64, elf_entry(), 0);
- fetch_and_execute()
+ try {
+ fetch_and_execute()
+ } catch {
+ Error_not_implemented(s) => print_string("Error: Not implemented: ", s),
+ Error_misaligned_access => print("Error: misaligned_access"),
+ Error_EBREAK => print("EBREAK"),
+ Error_internal_error => print("Error: internal error")
+ };
+ dump_state ()
}