diff options
| author | Prashanth Mundkur | 2018-04-20 17:35:48 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-04-20 17:36:49 -0700 |
| commit | 1b95665db9cf1deda3bfe243ed4038c47d1e940f (patch) | |
| tree | edc696c04df6634925d78fa0c18af6d29f3dc802 /riscv/main.sail | |
| parent | 8d74837e5b95866ed24795e81d1e685499067cfa (diff) | |
Add a riscv instruction printer for the execution log.
Diffstat (limited to 'riscv/main.sail')
| -rw-r--r-- | riscv/main.sail | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/riscv/main.sail b/riscv/main.sail index b686f768..66ac89bd 100644 --- a/riscv/main.sail +++ b/riscv/main.sail @@ -8,7 +8,7 @@ val elf_tohost = { function fetch_and_execute () = let tohost = __GetSlice_int(64, elf_tohost(), 0) in while true do { - print_bits("PC: ", PC); + print_bits("\nPC: ", PC); /* for now, always fetch a 32-bit value. this would need to change with privileged mode, since we could cross a page @@ -20,6 +20,11 @@ function fetch_and_execute () = 0b11 => (decode(instr), 4), _ => (decodeCompressed(instr[15 .. 0]), 2) }; + match (instr_ast, instr_sz) { + (Some(ast), 4) => print(BitStr(instr) ^ ": " ^ ast), + (Some(ast), 2) => print(BitStr(instr[15 .. 0]) ^ ": " ^ ast), + (_, _) => print(BitStr(instr) ^ ": no-decode") + }; /* check whether a compressed instruction is legal. */ if (misa.C() == 0b0 & (instr_sz == 2)) then { let t : sync_exception = |