diff options
| author | Robert Norton | 2016-04-27 12:54:16 +0100 |
|---|---|---|
| committer | Robert Norton | 2016-04-27 12:54:16 +0100 |
| commit | 654e9fbc68f6e253af41e91bb91edeaba204a9b8 (patch) | |
| tree | 9c488ab4f44f68301bd64168bfcb4e8b09b2257c /mips/mips_prelude.sail | |
| parent | d9f4c62a3e4ee6d74580a9168040b3dace7b384f (diff) | |
cheri: add translation and bounds checking of PC via PCC. Slightly clunky implementation for now and exceptions not properly handled.
Diffstat (limited to 'mips/mips_prelude.sail')
| -rw-r--r-- | mips/mips_prelude.sail | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/mips/mips_prelude.sail b/mips/mips_prelude.sail index 18eec9cc..801802de 100644 --- a/mips/mips_prelude.sail +++ b/mips/mips_prelude.sail @@ -185,7 +185,7 @@ function unit SignalExceptionBadAddr((Exception) ex, (bit[64]) badAddr) = typedef MemAccessType = enumerate {Instruction; LoadData; StoreData} typedef AccessLevel = enumerate {Kernel; Supervisor; User} -function (option<Exception>, option<bit[64]>) TranslateAddress ((bit[64]) vAddr, (MemAccessType) accessType) = +function (option<Exception>, option<bit[64]>) TLBTranslate ((bit[64]) vAddr, (MemAccessType) accessType) = { err := (if (accessType == StoreData) then Some(AdES) else Some(AdEL)); switch(vAddr[63..62]) { @@ -203,7 +203,7 @@ function (option<Exception>, option<bit[64]>) TranslateAddress ((bit[64]) vAddr, } function bit[64] TranslateOrExit((bit[64]) vAddr, (MemAccessType) accessType) = - switch (TranslateAddress(vAddr, accessType)) { + switch (TLBTranslate(vAddr, accessType)) { case ((Some(ex)), _) -> (exit (SignalExceptionBadAddr (ex, vAddr))) case (_, (Some(pAddr))) -> pAddr } |
