diff options
| author | Shaked Flur | 2020-11-25 16:21:04 +0000 |
|---|---|---|
| committer | Shaked Flur | 2020-11-25 16:21:04 +0000 |
| commit | 1c425ffde61d7dafa989a9c53df0eba6c0672248 (patch) | |
| tree | 6b1938fadc4c3f37f735da6003b1fe78c9f8a1fa /aarch64_small | |
| parent | 294cd644532560a080d3ca527043b47dd97115ad (diff) | |
Fix BLR
Reorder the read and write of registers to allow MP+dmb.sy+blr-addr.
Diffstat (limited to 'aarch64_small')
| -rw-r--r-- | aarch64_small/armV8.sail | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/aarch64_small/armV8.sail b/aarch64_small/armV8.sail index 40a28d35..03bca319 100644 --- a/aarch64_small/armV8.sail +++ b/aarch64_small/armV8.sail @@ -679,9 +679,11 @@ function clause decodeUnconditionalBranchRegister (0b1101011@0b00@(op : bits(2)) } function clause execute (BranchRegister(n,branch_type)) = { + /* ARM: the 'wX(30)' happens after the 'rX(n)'. + We reorder those to allow MP+dmb.sy+blr-addr */ + if branch_type == BranchType_CALL then wX(30) = rPC() + 4; target : bits(64) = rX(n); - if branch_type == BranchType_CALL then wX(30) = rPC() + 4; BranchTo(target, branch_type); } |