From 1c425ffde61d7dafa989a9c53df0eba6c0672248 Mon Sep 17 00:00:00 2001
From: Shaked Flur
Date: Wed, 25 Nov 2020 16:21:04 +0000
Subject: Fix BLR

Reorder the read and write of registers to allow MP+dmb.sy+blr-addr.
---
 aarch64_small/armV8.sail | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'aarch64_small')

diff --git a/aarch64_small/armV8.sail b/aarch64_small/armV8.sail
index 40a28d35..03bca319 100644
--- a/aarch64_small/armV8.sail
+++ b/aarch64_small/armV8.sail
@@ -679,9 +679,11 @@ function clause decodeUnconditionalBranchRegister (0b1101011@0b00@(op : bits(2))
 }
 
 function clause execute (BranchRegister(n,branch_type)) = {
+  /* ARM: the 'wX(30)' happens after the 'rX(n)'.
+  We reorder those to allow MP+dmb.sy+blr-addr */
+  if branch_type == BranchType_CALL then wX(30) = rPC() + 4;
   target : bits(64) = rX(n);
 
-  if branch_type == BranchType_CALL then wX(30) = rPC() + 4;
   BranchTo(target, branch_type);
 }
 
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