diff options
| author | Austin Seipp | 2019-02-06 14:17:50 -0600 |
|---|---|---|
| committer | GitHub | 2019-02-06 14:17:50 -0600 |
| commit | 949cbcbc9debc364771ea76dff4d43a36a50ca5b (patch) | |
| tree | faacaac751c3a59aa7380fe0aab17d5e795a4cef /README.md | |
| parent | 0c42ba405004f697a643135212d74a4369eb61df (diff) | |
README: add a link to my RISC-V implementation
Signed-off-by: Austin Seipp <aseipp@pobox.com>
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -62,6 +62,8 @@ Sail is currently being used for ARM, RISC-V, MIPS, CHERI-MIPS, IBM Power, and x * [Sail x86 ISA model, handwritten](https://github.com/rems-project/sail/tree/sail2/x86). This is a handwritten user-mode fragment. +* [Sail 32-bit RISC-V model, partially handwritten and partially generated](https://github.com/thoughtpolice/rv32-sail). This currently implements a fragment of the machine mode (-M) specification for RV32IM. (Developed independently of the full RISC-V model for the REMS project.) + The hand-written ARMv8-A, IBM POWER, and x86 models are currently not in sync with the latest version of Sail, which is the (default) sail2 branch on Github. These and the RISC-V model are integrated with our [RMEM](http://www.cl.cam.ac.uk/users/pes20/rmem) tool for concurrency semantics. |