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authorPrashanth Mundkur2018-04-17 17:37:09 -0700
committerPrashanth Mundkur2018-04-17 17:37:47 -0700
commitefd8234cbac39bcf4ca6498057be5115cfda7fe7 (patch)
tree6f7ab0a11db9944f7eb3eee731dbd5c62596fc24
parentac0840873d07b475ce9bdcb0a53ead7e377f1dcd (diff)
Add platform initialization for the new bits of machine state.
-rw-r--r--riscv/riscv_sys.sail7
-rw-r--r--riscv/riscv_types.sail7
2 files changed, 14 insertions, 0 deletions
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail
index 66d8a7c8..f81a7ebd 100644
--- a/riscv/riscv_sys.sail
+++ b/riscv/riscv_sys.sail
@@ -649,5 +649,12 @@ function handle_exception_ctl(cur_priv : Privilege, ctl : ctl_result,
function init_sys () : unit -> unit = {
cur_privilege = Machine;
+ misa->MXL() = arch_to_bits(RV64);
misa->C() = true;
+ misa->U() = true;
+ misa->S() = true;
+
+ mstatus->SXL() = misa.MXL();
+ mstatus->UXL() = misa.MXL();
+ mstatus->SD() = false;
}
diff --git a/riscv/riscv_types.sail b/riscv/riscv_types.sail
index 2d184042..78b0ea89 100644
--- a/riscv/riscv_types.sail
+++ b/riscv/riscv_types.sail
@@ -61,6 +61,13 @@ function architecture(a : arch_xlen) -> option(Architecture) = {
_ => None()
}
}
+function arch_to_bits(a : Architecture) -> arch_xlen = {
+ match (a) {
+ RV32 => 0b01,
+ RV64 => 0b10,
+ RV128 => 0b11
+ }
+}
/* privilege levels */