Initial

Added work on RV64 I core to date, including tb

1 files changed, 114 insertions, 0 deletions

diff --git a/core/aluctrl.v b/core/aluctrl.v
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+/**
+ This file contains ALU control logic.
+ 
+ * The ALU control unit
+ *
+ * Input:  aluop      00 for ld/st, 10 for R-type, 01 for branch
+ * Input:  funct7     The most significant bits of the instruction
+ * Input:  funct3     The middle three bits of the instruction (12-14)
+ * Output: operation  What we want the ALU to do.
+ **/
+
+module aluctrl(
+	       input wire [1:0] aluop,
+	       input wire 	itype,
+	       input wire [6:0] funct7,
+	       input wire [2:0] funct3,
+	       output reg [3:0] operation
+	       );
+   
+   always @* begin
+      case (aluop)
+	2'b00:
+	  operation = 4'b0010;
+	2'b10: begin
+	   case (funct3)
+	     3'b000: begin
+		if (itype == 1'b1 || funct7 == 7'b0000000)
+		  operation = 4'b0010; // add
+		else
+		  operation = 4'b0011; //sub
+	     end
+	     3'b001: operation = 4'b1001; // sll
+	     3'b010: operation = 4'b1000; // slt
+	     3'b011: operation = 4'b0101; // sltu
+	     3'b100: operation = 4'b0110; // xor
+	     3'b101: begin
+		if (funct7 == 7'b0000000)
+		  assign operation = 4'b0111; // srl
+		else
+		  assign operation = 4'b0100; // sra
+	     end
+	     4'b110: operation = 4'b0001; // or
+	     4'b111: operation = 4'b0000;	     
+	   endcase // case (funct3)
+	end // case: 2'b10	
+        2'b01: begin
+	   case (funct3)	     
+	     3'b000: operation = 4'b1101; // beq
+	     3'b001: operation = 4'b1110; // bne
+	     3'b100: operation = 4'b1000; // blt
+	     3'b101: operation = 4'b1011; // bge
+	     3'b110: operation = 4'b0101; // bltu
+	     3'b111: operation = 4'b1100; // bgeu
+	     default: operation = 4'b1111; // invalid
+	   endcase // case (funct3)
+	end // case: 2'b01	
+	default: operation = 4'b1111; // invalid
+      endcase // case (aluop)
+   end // always @ *
+   
+   // Direct translation from dino
+   // if (aluop == 2'b00) begin // ld/st
+   // 	 assign operation = 4'b0010;
+   // end
+   // else if (aluop == 2'b10) begin
+   // 	 if (funct3 == 3'b000) begin // R-type
+   // 	    if (itype == 1'b1 || funct7 == 7'b0000000)
+   // 	      assign operation = 4'b0010; // add
+   // 	    else
+   // 	      assign operation = 4'b0011; //sub
+   // 	 end	 
+   // 	 else if (funct3 == 3'b001)
+   // 	   assign operation = 4'b1001; // sll
+   // 	 else if (funct3 == 3'b010)
+   // 	   assign operation = 4'b1000; // slt
+   // 	 else if (funct3 == 3'b011)
+   // 	   assign operation = 4'b0101; // sltu
+   // 	 else if (funct3 == 3'b100)
+   // 	   assign operation = 4'b0110; // xor
+   
+   // 	 else if (funct3 == 3'b101) begin
+   // 	    if (func7 == 7'b0000000)
+   // 	      assign operation = 4'b0111; // srl
+   // 	    else
+   // 	      assign operation = 4'b0100; // sra
+   // 	 end
+   // 	 else if (funct3 == 4'b110)
+   // 	   assign operation = 4'b0001; // or
+   // 	 else
+   // 	   assign operation = 4'b000;	 
+   // end
+   // else if (aluop == 2'b01) begin // branches
+   // 	 if (funct3 == 3'b000)
+   // 	   assign operation = 4'b1101; // beq
+   // 	 else if (funct3 == 3'b001)
+   // 	   assign operation = 4'b1110; // bne
+   // 	 else if (funct3 == 3'b100)
+   // 	   assign operation = 4'b1000; // blt
+   // 	 else if (funct3 == 3'b101)
+   // 	   assign operation = 4'b1011; // bge
+   // 	 else if (funct3 == 3'b110)
+   // 	   assign operation = 4'b0101; // bltu
+   // 	 else if (funct3 == 3'b111)
+   // 	   assign operation = 4'b1100; // bgeu
+   // 	 else
+   // 	   assign operation = 4'b1111; // invalid
+   // end
+   // else
+   // 	assign operation = 4'b1111; // invalid
+   // end // always @ *
+   
+endmodule // aluctrl
+
+