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| author | Aditya Naik | 2021-04-25 17:55:54 -0400 |
|---|---|---|
| committer | Aditya Naik | 2021-04-25 17:55:54 -0400 |
| commit | 439c12b39967eeee976d406d5bc99bee551cbd0c (patch) | |
| tree | 838fc34a1052d2802c2315e0ce9d3807d98a34cd /pcb/base/openmano-hw-cache.lib | |
| parent | aab29bc8d909ddf5a3151073b7003bf84ee7e844 (diff) | |
Routed tracks on PCB - DRC passed.
Changed local and global bus labels for clarity. Fixed UART RX/TX in base schematic.
Diffstat (limited to 'pcb/base/openmano-hw-cache.lib')
0 files changed, 0 insertions, 0 deletions