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path: root/ports/stm32/boards/pllvalues.py
AgeCommit message (Expand)Author
2021-04-20stm32/boards/pllvalues.py: Support wider range of PLL values for F413.Damien George
2021-04-07stm32/boards/pllvalues.py: Relax PLLQ constraints on STM32F413 MCUs.Damien George
2020-02-28all: Reformat C and Python source code with tools/codeformat.py.Damien George
2020-01-31stm32/powerctrl: Improve support for changing system freq on H7 MCUs.Damien George
2019-06-25stm32/boards/pllvalues.py: Support HSx_VALUE defined without uint32_t.Damien George
2019-05-31stm32/boards/pllvalues.py: Search nested headers for HSx_VALUE defines.Damien George
2019-05-02stm32/powerctrl: Support changing frequency when HSI is clock source.Damien George
2018-09-11stm32: For MCUs that have PLLSAI allow to set SYSCLK at 2MHz increments.Damien George
2017-09-06ports: Make new ports/ sub-directory and move all ports there.Damien George