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Diffstat (limited to 'stmhal/hal/src/stm32f4xx_ll_sdmmc.c')
-rw-r--r--stmhal/hal/src/stm32f4xx_ll_sdmmc.c83
1 files changed, 21 insertions, 62 deletions
diff --git a/stmhal/hal/src/stm32f4xx_ll_sdmmc.c b/stmhal/hal/src/stm32f4xx_ll_sdmmc.c
index aaedb7062..9e0b60903 100644
--- a/stmhal/hal/src/stm32f4xx_ll_sdmmc.c
+++ b/stmhal/hal/src/stm32f4xx_ll_sdmmc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_sdmmc.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0
+ * @date 19-June-2014
* @brief SDMMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -66,8 +66,8 @@
(+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO
peripheral.
- (+) Enable the Power ON State using the HAL_SDIO_PowerState_ON(hsdio)
- function and disable it using the function HAL_SDIO_PowerState_OFF(hsdio).
+ (+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx)
+ function and disable it using the function HAL_SDIO_PowerState_OFF(SDIOx).
(+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
@@ -81,8 +81,8 @@
__SDIO_DMA_DISABLE().
(+) To control the CPSM (Command Path State Machine) and send
- commands to the card use the HAL_SDIO_SendCommand(),
- HAL_SDIO_GetCommandResponse() and HAL_SDIO_GetResponse() functions. First, user has
+ commands to the card use the SDIO_SendCommand(SDIOx),
+ SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
to fill the command structure (pointer to SDIO_CmdInitTypeDef) according
to the selected command to be sent.
The parameters that should be filled are:
@@ -93,13 +93,13 @@
(++) CPSM Status (Enable or Disable).
-@@- To check if the command is well received, read the SDIO_CMDRESP
- register using the HAL_SDIO_GetCommandResponse().
+ register using the SDIO_GetCommandResponse().
The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
- HAL_SDIO_GetResponse() function.
+ SDIO_GetResponse() function.
(+) To control the DPSM (Data Path State Machine) and send/receive
- data to/from the card use the HAL_SDIO_DataConfig(), HAL_SDIO_GetDataCounter(),
- HAL_SDIO_ReadFIFO(), HAL_SDIO_WriteFIFO() and HAL_SDIO_GetFIFOCount() functions.
+ data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
+ SDIO_ReadFIFO(), DIO_WriteFIFO() and SDIO_GetFIFOCount() functions.
*** Read Operations ***
=======================
@@ -135,9 +135,9 @@
(++) DPSM Status (Enable or Disable)
(#) Configure the SDIO resources to send the data to the card according to
- selected transfer mode (Refer to Step 8, 9 and 10).
+ selected transfer mode.
- (#) Send the selected Write command (refer to step 11).
+ (#) Send the selected Write command.
(#) Use the SDIO flags/interrupts to check the transfer status.
@@ -219,7 +219,7 @@
*/
HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
{
- __IO uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));
@@ -230,12 +230,6 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));
- /* Get the SDIO CLKCR value */
- tmpreg = SDIOx->CLKCR;
-
- /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
- tmpreg &= CLKCR_CLEAR_MASK;
-
/* Set SDIO configuration parameters */
tmpreg |= (Init.ClockEdge |\
Init.ClockBypass |\
@@ -246,7 +240,7 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
);
/* Write to SDIO CLKCR */
- SDIOx->CLKCR = tmpreg;
+ MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
return HAL_OK;
}
@@ -275,7 +269,6 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
/**
* @brief Read data (word) from Rx FIFO in blocking mode (polling)
* @param SDIOx: Pointer to SDIO register base
- * @param ReadData: Data to read
* @retval HAL status
*/
uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
@@ -325,7 +318,7 @@ HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
{
/* Set power state to ON */
- SDIOx->POWER = (uint32_t)0x00000003;
+ SDIOx->POWER = SDIO_POWER_PWRCTRL;
return HAL_OK;
}
@@ -354,7 +347,7 @@ HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
*/
uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx)
{
- return (SDIOx->POWER & (~PWR_PWRCTRL_MASK));
+ return (SDIOx->POWER & SDIO_POWER_PWRCTRL);
}
/**
@@ -377,14 +370,7 @@ HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDI
/* Set the SDIO Argument value */
SDIOx->ARG = SDIO_CmdInitStruct->Argument;
-
- /* SDIO CMD Configuration */
- /* Get the SDIO CMD value */
- tmpreg = SDIOx->CMD;
-
- /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
- tmpreg &= CMD_CLEAR_MASK;
-
+
/* Set SDIO command parameters */
tmpreg |= (uint32_t)(SDIO_CmdInitStruct->CmdIndex |\
SDIO_CmdInitStruct->Response |\
@@ -392,7 +378,7 @@ HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDI
SDIO_CmdInitStruct->CPSM);
/* Write to SDIO CMD register */
- SDIOx->CMD = tmpreg;
+ MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg);
return HAL_OK;
}
@@ -456,21 +442,14 @@ HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDI
/* Set the SDIO DataLength value */
SDIOx->DLEN = SDIO_DataInitStruct->DataLength;
-/* SDIO DCTRL Configuration */
- /* Get the SDIO DCTRL value */
- tmpreg = SDIOx->DCTRL;
-
- /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
- tmpreg &= DCTRL_CLEAR_MASK;
-
/* Set the SDIO data configuration parameters */
tmpreg |= (uint32_t)(SDIO_DataInitStruct->DataBlockSize |\
SDIO_DataInitStruct->TransferDir |\
SDIO_DataInitStruct->TransferMode |\
SDIO_DataInitStruct->DPSM);
-
+
/* Write to SDIO DCTRL */
- SDIOx->DCTRL = tmpreg;
+ MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
return HAL_OK;
@@ -488,7 +467,7 @@ uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)
/**
* @brief Get the FIFO data
- * @param hsdio: SDIO handle
+ * @param SDIOx: Pointer to SDIO register base
* @retval Data received
*/
uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
@@ -515,26 +494,6 @@ HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
return HAL_OK;
}
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SDIO_Group3 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permit to get in runtime the status of the SDIO peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
/**
* @}
*/
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-29 22:51:52 +0000