diff options
Diffstat (limited to 'stmhal/hal/inc/stm32f4xx_hal_rcc.h')
| -rw-r--r-- | stmhal/hal/inc/stm32f4xx_hal_rcc.h | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/stmhal/hal/inc/stm32f4xx_hal_rcc.h b/stmhal/hal/inc/stm32f4xx_hal_rcc.h index 08b0ebd62..be558b357 100644 --- a/stmhal/hal/inc/stm32f4xx_hal_rcc.h +++ b/stmhal/hal/inc/stm32f4xx_hal_rcc.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f4xx_hal_rcc.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0
+ * @date 19-June-2014
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
@@ -67,16 +67,16 @@ typedef struct uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
This parameter must be a value of @ref RCC_PLL_Clock_Source */
- uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock
+ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
- uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock
+ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
- uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK)
- This parameter must be a value of @ref RCC_PLLP_Clock_Divider. */
+ uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
+ This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
- uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks
+ uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
}RCC_PLLInitTypeDef;
@@ -655,11 +655,15 @@ typedef struct /** @brief Force or release AHB2 peripheral reset.
*/
#define __AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
-#define __OTGFS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+#define __USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
#define __AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
-#define __OTGFS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+#define __USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+/* alias define maintained for legacy */
+#define __OTGFS_FORCE_RESET __USB_OTG_FS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __USB_OTG_FS_RELEASE_RESET
+
#define __RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
#define __RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
@@ -764,9 +768,13 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
*/
-#define __OTGFS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
-#define __OTGFS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+/* alias define maintained for legacy */
+#define __OTGFS_CLK_SLEEP_ENABLE __USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __USB_OTG_FS_CLK_SLEEP_DISABLE
#define __RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
#define __RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
@@ -1042,11 +1050,6 @@ typedef struct */
#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
-/** @defgroup RCC_Flags_Interrupts_Management
- * @brief macros to manage the specified RCC Flags and interrupts.
- * @{
- */
-
/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
* the selected interrupts).
* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
@@ -1126,9 +1129,6 @@ typedef struct */
#define RCC_FLAG_MASK ((uint8_t)0x1F)
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
-/**
- * @}
- */
#define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
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