diff options
Diffstat (limited to 'stmhal/cmsis/devinc/stm32f437xx.h')
| -rw-r--r-- | stmhal/cmsis/devinc/stm32f437xx.h | 43 |
1 files changed, 40 insertions, 3 deletions
diff --git a/stmhal/cmsis/devinc/stm32f437xx.h b/stmhal/cmsis/devinc/stm32f437xx.h index 6f724a48d..c261d1a0e 100644 --- a/stmhal/cmsis/devinc/stm32f437xx.h +++ b/stmhal/cmsis/devinc/stm32f437xx.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f437xx.h
* @author MCD Application Team
- * @version V2.0.0
- * @date 18-February-2014
+ * @version V2.1.0
+ * @date 19-June-2014
* @brief CMSIS STM32F437xx Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -1073,7 +1073,7 @@ USB_OTG_HostChannelTypeDef; /** @addtogroup Peripheral_memory_map
* @{
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 2 MB) base address in the alias region */
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
@@ -1087,6 +1087,8 @@ USB_OTG_HostChannelTypeDef; #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
+#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
@@ -5094,6 +5096,25 @@ USB_OTG_HostChannelTypeDef; #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
/******************************************************************************/
/* */
/* HASH */
@@ -5298,6 +5319,8 @@ USB_OTG_HostChannelTypeDef; /* Legacy define */
#define PWR_CR_PMODE PWR_CR_VOS
+#define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
+#define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
/******************* Bit definition for PWR_CSR register ********************/
#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
@@ -8831,6 +8854,20 @@ USB_OTG_HostChannelTypeDef; /****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define FSMC_IRQn FMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FSMC_IRQHandler FMC_IRQHandler
+
/**
* @}
*/
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