diff options
Diffstat (limited to 'ports/stm32/system_stm32.c')
| -rw-r--r-- | ports/stm32/system_stm32.c | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/ports/stm32/system_stm32.c b/ports/stm32/system_stm32.c index 77875f32c..6c24ee417 100644 --- a/ports/stm32/system_stm32.c +++ b/ports/stm32/system_stm32.c @@ -107,21 +107,21 @@ void __fatal_error(const char *msg); * @{ */ -#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7) +#if defined(STM32F4) || defined(STM32F7) #define CONFIG_RCC_CR_1ST (RCC_CR_HSION) #define CONFIG_RCC_CR_2ND (RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON) #define CONFIG_RCC_PLLCFGR (0x24003010) -#if defined(MCU_SERIES_F4) +#if defined(STM32F4) const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; -#elif defined(MCU_SERIES_F7) +#elif defined(STM32F7) const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; #endif -#elif defined(MCU_SERIES_L4) +#elif defined(STM32L4) #define CONFIG_RCC_CR_1ST (RCC_CR_MSION) #define CONFIG_RCC_CR_2ND (RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_HSION | RCC_CR_PLLON) @@ -263,9 +263,9 @@ void SystemInit(void) RCC->CR &= (uint32_t)0xFFFBFFFF; /* Disable all interrupts */ - #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7) + #if defined(STM32F4) || defined(STM32F7) RCC->CIR = 0x00000000; - #elif defined(MCU_SERIES_L4) || defined(STM32H7) + #elif defined(STM32L4) || defined(STM32H7) RCC->CIER = 0x00000000; #endif @@ -373,7 +373,7 @@ void SystemClock_Config(void) RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; #endif - #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7) || defined(STM32H7) + #if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) /* Enable Power Control clock */ #if defined(STM32H7) @@ -386,7 +386,7 @@ void SystemClock_Config(void) clocked below the maximum system frequency, to update the voltage scaling value regarding system frequency refer to product datasheet. */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - #elif defined(MCU_SERIES_L4) + #elif defined(STM32L4) // Configure LSE Drive Capability __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); #endif @@ -398,7 +398,7 @@ void SystemClock_Config(void) #endif /* Enable HSE Oscillator and activate PLL with HSE as source */ - #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7) || defined(STM32H7) + #if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.HSIState = RCC_HSI_OFF; @@ -406,7 +406,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.CSIState = RCC_CSI_OFF; #endif RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - #elif defined(MCU_SERIES_L4) + #elif defined(STM32L4) RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI; RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.MSIState = RCC_MSI_ON; @@ -424,9 +424,9 @@ void SystemClock_Config(void) RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; #if defined(MICROPY_HW_CLK_LAST_FREQ) && MICROPY_HW_CLK_LAST_FREQ - #if defined(MCU_SERIES_F7) + #if defined(STM32F7) #define FREQ_BKP BKP31R - #elif defined(MCU_SERIES_L4) + #elif defined(STM32L4) #error Unsupported Processor #else #define FREQ_BKP BKP19R @@ -470,7 +470,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLN = MICROPY_HW_CLK_PLLN; RCC_OscInitStruct.PLL.PLLP = MICROPY_HW_CLK_PLLP; RCC_OscInitStruct.PLL.PLLQ = MICROPY_HW_CLK_PLLQ; - #if defined(MCU_SERIES_L4) || defined(STM32H7) + #if defined(STM32L4) || defined(STM32H7) RCC_OscInitStruct.PLL.PLLR = MICROPY_HW_CLK_PLLR; #endif @@ -480,11 +480,11 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLFRACN = 0; #endif - #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7) + #if defined(STM32F4) || defined(STM32F7) RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - #elif defined(MCU_SERIES_L4) + #elif defined(STM32L4) RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; @@ -519,7 +519,7 @@ void SystemClock_Config(void) } #endif -#if defined(MCU_SERIES_F7) +#if defined(STM32F7) /* Activate the OverDrive to reach the 200 MHz Frequency */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { @@ -550,14 +550,14 @@ void SystemClock_Config(void) HAL_PWREx_EnableUSBVoltageDetector(); #endif -#if defined(MCU_SERIES_F7) +#if defined(STM32F7) // The DFU bootloader changes the clocksource register from its default power // on reset value, so we set it back here, so the clocksources are the same // whether we were started from DFU or from a power on reset. RCC->DCKCFGR2 = 0; #endif -#if defined(MCU_SERIES_L4) +#if defined(STM32L4) // Enable MSI-Hardware auto calibration mode with LSE HAL_RCCEx_EnableMSIPLLMode(); @@ -600,7 +600,7 @@ void SystemClock_Config(void) } void HAL_MspInit(void) { -#if defined(MCU_SERIES_F7) || defined(STM32H7) +#if defined(STM32F7) || defined(STM32H7) /* Enable I-Cache */ SCB_EnableICache(); |