diff options
| author | Damien George | 2014-10-04 01:54:02 +0100 |
|---|---|---|
| committer | Damien George | 2014-10-04 01:54:02 +0100 |
| commit | c568a2b44387bee14ea5f427a6e9b736eb1b5345 (patch) | |
| tree | 54b99c2ed5f3abfc3ab88e06941869bdc842ba12 /stmhal/hal | |
| parent | 1f2558d647cfd62a5835a0bed0decfdf82149a09 (diff) | |
stmhal: Adjust computation of SYSCLK to retain precision.
Diffstat (limited to 'stmhal/hal')
| -rw-r--r-- | stmhal/hal/src/stm32f4xx_hal_rcc.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/stmhal/hal/src/stm32f4xx_hal_rcc.c b/stmhal/hal/src/stm32f4xx_hal_rcc.c index bda08db3f..dbebbf182 100644 --- a/stmhal/hal/src/stm32f4xx_hal_rcc.c +++ b/stmhal/hal/src/stm32f4xx_hal_rcc.c @@ -972,7 +972,12 @@ uint32_t HAL_RCC_GetSysClockFreq(void) if (__RCC_PLLSRC() != 0)
{
/* HSE used as PLL clock source */
- pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+ //pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+ // dpgeorge: Adjust the way the arithmetic is done so it retains
+ // precision for the case that pllm doesn't evenly divide HSE_VALUE.
+ // Must be sure not to overflow, so divide by 4 first. HSE_VALUE
+ // should be a multiple of 4 (being a multiple of 100 is enough).
+ pllvco = ((HSE_VALUE / 4) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))) / pllm * 4;
}
else
{
|