stmhal - fixed up adc stuff

Added support for the ADC channels and mappings to make_pins.py

I'm not sure if the hal properly deals with the channel 16/18 differences
between the 40x and 42x. It seems to deal with it partially. This particular
aspect will need testing on a 42x or 43x.

3 files changed, 84 insertions, 33 deletions

diff --git a/stmhal/boards/make-pins.py b/stmhal/boards/make-pins.py
index 8c1bedbf0..ee1193498 100755
--- a/stmhal/boards/make-pins.py
+++ b/stmhal/boards/make-pins.py
@@ -94,6 +94,8 @@ class Pin(object):
         self.alt_fn = []
         self.board_name = None
         self.alt_fn_count = 0
+        self.adc_num = 0
+        self.adc_channel = 0
 
     def port_letter(self):
         return chr(self.port + ord('A'))
@@ -101,6 +103,15 @@ class Pin(object):
     def pin_name(self):
         return '{:s}{:d}'.format(self.port_letter(), self.pin)
 
+    def parse_adc(self, adc_str):
+        if (adc_str[:3] != 'ADC'):
+            return
+        (adc,channel) = adc_str.split('_')
+        for idx in range(3, len(adc)):
+            adc_num = int(adc[idx]) # 1, 2, or 3
+            self.adc_num |= (1 << (adc_num - 1))
+        self.adc_channel = int(channel[2:])
+
     def parse_af(self, af_idx, af_strs_in):
         if len(af_strs_in) == 0:
             return
@@ -113,10 +124,22 @@ class Pin(object):
             if alt_fn.is_supported():
                 self.alt_fn_count += 1
 
-    def alt_fn_name(self):
-        if self.alt_fn_count > 0:
-            return 'pin_{:s}_af'.format(self.pin_name())
-        return 'NULL'
+    def alt_fn_name(self, null_if_0=False):
+        if null_if_0 and self.alt_fn_count == 0:
+            return 'NULL'
+        return 'pin_{:s}_af'.format(self.pin_name())
+
+    def adc_num_str(self):
+        str = ''
+        for adc_num in range(1,4):
+            if self.adc_num & (1 << (adc_num - 1)):
+                if len(str) > 0:
+                    str += ' | '
+                str += 'PIN_ADC'
+                str += chr(ord('0') + adc_num)
+        if len(str) == 0:
+            str = '0'
+        return str
 
     def print(self):
         if self.alt_fn_count == 0:
@@ -128,9 +151,10 @@ class Pin(object):
             print("// ",  end='')
         print('};')
         print('')
-        print('const pin_obj_t pin_{:s} = PIN({:s}, {:d}, {:d}, {:s});'.format(
+        print('const pin_obj_t pin_{:s} = PIN({:s}, {:d}, {:d}, {:s}, {:s}, {:d});'.format(
             self.pin_name(), self.port_letter(), self.pin,
-            self.alt_fn_count, self.alt_fn_name()))
+            self.alt_fn_count, self.alt_fn_name(null_if_0=True),
+            self.adc_num_str(), self.adc_channel))
         print('')
 
     def print_header(self, hdr_file):
@@ -162,7 +186,10 @@ class Pins(object):
                     continue
                 pin = Pin(port_num, pin_num)
                 for af_idx in range(af_col, len(row)):
-                    pin.parse_af(af_idx - af_col, row[af_idx])
+                    if af_idx < af_col + 16:
+                        pin.parse_af(af_idx - af_col, row[af_idx])
+                    elif af_idx == af_col + 16:
+                        pin.parse_adc(row[af_idx])
                 self.pins.append(pin)
 
     def parse_board_file(self, filename):
@@ -198,11 +225,30 @@ class Pins(object):
         print('')
         self.print_named('board', self.board_pins)
 
+    def print_adc(self, adc_num):
+        print('');
+        print('const pin_obj_t * const pin_adc{:d}[] = {{'.format(adc_num))
+        for channel in range(16):
+            adc_found = False
+            for pin in self.pins:
+                if (pin.board_name and
+                    (pin.adc_num & (1 << (adc_num - 1))) and (pin.adc_channel == channel)):
+                    print('  &pin_{:s}, // {:d}'.format(pin.pin_name(), channel))
+                    adc_found = True
+                    break
+            if not adc_found:
+                print('  NULL,    // {:d}'.format(channel))
+        print('};')
+
+
     def print_header(self, hdr_filename):
         with open(hdr_filename, 'wt') as hdr_file:
             for pin in self.pins:
                 if pin.board_name:
                     pin.print_header(hdr_file)
+            hdr_file.write('extern const pin_obj_t * const pin_adc1[];\n')
+            hdr_file.write('extern const pin_obj_t * const pin_adc2[];\n')
+            hdr_file.write('extern const pin_obj_t * const pin_adc3[];\n')
 
 
 def main():
@@ -254,6 +300,9 @@ def main():
         with open(args.prefix_filename, 'r') as prefix_file:
             print(prefix_file.read())
     pins.print()
+    pins.print_adc(1)
+    pins.print_adc(2)
+    pins.print_adc(3)
     pins.print_header(args.hdr_filename)
 
 
diff --git a/stmhal/boards/stm32f4xx-af.csv b/stmhal/boards/stm32f4xx-af.csv
index fde7fcfc1..0a21fc87d 100644
--- a/stmhal/boards/stm32f4xx-af.csv
+++ b/stmhal/boards/stm32f4xx-af.csv
@@ -1,13 +1,13 @@
 Port,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15
-,,SYS,TIM1/2,TIM3/4/5,TIM8/9/10/11,I2C1/2/3,SPI1/SPI2/I2S2/I2S2ext,SPI3/I2Sext/I2S3,USART1/2/3/I2S3ext,UART4/5/USART6,CAN1/CAN2/TIM12/13/14,OTG_FS/OTG_HS,ETH,FSMC/SDIO/OTG_FS,DCMI,,
-PortA,PA0,,TIM2_CH1_ETR,TIM5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,,ETH_MII_CRS,,,,EVENTOUT
-PortA,PA1,,TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,,,ETH_MII_RX_CLK/ETH_RMII__REF_CLK,,,,EVENTOUT
-PortA,PA2,,TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,,,,ETH_MDIO,,,,EVENTOUT
-PortA,PA3,,TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,OTG_HS_ULPI_D0,ETH_MII_COL,,,,EVENTOUT
-PortA,PA4,,,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,OTG_HS_SOF,DCMI_HSYNC,,EVENTOUT
-PortA,PA5,,TIM2_CH1_ETR,,TIM8_CH1N,,SPI1_SCK,,,,,OTG_HS_ULPI_CK,,,,,EVENTOUT
-PortA,PA6,,TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,,TIM13_CH1,,,,DCMI_PIXCK,,EVENTOUT
-PortA,PA7,,TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI,,,,TIM14_CH1,,ETH_MII_RX_DV/ETH_RMII_CRS_DV,,,,EVENTOUT
+,,SYS,TIM1/2,TIM3/4/5,TIM8/9/10/11,I2C1/2/3,SPI1/SPI2/I2S2/I2S2ext,SPI3/I2Sext/I2S3,USART1/2/3/I2S3ext,UART4/5/USART6,CAN1/CAN2/TIM12/13/14,OTG_FS/OTG_HS,ETH,FSMC/SDIO/OTG_FS,DCMI,,,ADC
+PortA,PA0,,TIM2_CH1_ETR,TIM5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,,ETH_MII_CRS,,,,EVENTOUT,ADC123_IN0
+PortA,PA1,,TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,,,ETH_MII_RX_CLK/ETH_RMII__REF_CLK,,,,EVENTOUT,ADC123_IN1
+PortA,PA2,,TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,,,,ETH_MDIO,,,,EVENTOUT,ADC123_IN2
+PortA,PA3,,TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,OTG_HS_ULPI_D0,ETH_MII_COL,,,,EVENTOUTADC123_IN3
+PortA,PA4,,,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,OTG_HS_SOF,DCMI_HSYNC,,EVENTOUT,ADC12_IN4
+PortA,PA5,,TIM2_CH1_ETR,,TIM8_CH1N,,SPI1_SCK,,,,,OTG_HS_ULPI_CK,,,,,EVENTOUT,ADC12_IN5
+PortA,PA6,,TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,,TIM13_CH1,,,,DCMI_PIXCK,,EVENTOUT,ADC12_IN6
+PortA,PA7,,TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI,,,,TIM14_CH1,,ETH_MII_RX_DV/ETH_RMII_CRS_DV,,,,EVENTOUT,ADC12_IN7
 PortA,PA8,MCO1,TIM1_CH1,,,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,,,,,EVENTOUT
 PortA,PA9,,TIM1_CH2,,,I2C3_SMBA,,,USART1_TX,,,,,,DCMI_D0,,EVENTOUT
 PortA,PA10,,TIM1_CH3,,,,,,USART1_RX,,,OTG_FS_ID,,,DCMI_D1,,EVENTOUT
@@ -16,8 +16,8 @@ PortA,PA12,,TIM1_ETR,,,,,,USART1_RTS,,CAN1_TX,OTG_FS_DP,,,,,EVENTOUT
 PortA,PA13,JTMS-SWDIO,,,,,,,,,,,,,,,EVENTOUT
 PortA,PA14,JTCK-SWCLK,,,,,,,,,,,,,,,EVENTOUT
 PortA,PA15,JTDI,TIM2_CH1/TIM2_ETR,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,,,,,,,,,EVENTOUT
-PortB,PB0,,TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,,,,,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,,EVENTOUT
-PortB,PB1,,TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,,,,,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,,EVENTOUT
+PortB,PB0,,TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,,,,,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,,EVENTOUT,AC12_IN8
+PortB,PB1,,TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,,,,,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,,EVENTOUT,ADC12_IN9
 PortB,PB2,,,,,,,,,,,,,,,,EVENTOUT
 PortB,PB3,JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCKI2S3_CK,,,,,,,,,EVENTOUT
 PortB,PB4,NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,I2S3ext_SD,,,,,,,,EVENTOUT
@@ -32,12 +32,12 @@ PortB,PB12,,TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,,CAN2_RX,OTG_HS_UL
 PortB,PB13,,TIM1_CH1N,,,,SPI2_SCKI2S2_CK,,USART3_CTS,,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT
 PortB,PB14,,TIM1_CH2N,,TIM8_CH2N,,SPI2_MISO,I2S2ext_SD,USART3_RTS,,TIM12_CH1,,,OTG_HS_DM,,,EVENTOUT
 PortB,PB15,RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,,SPI2_MOSI/I2S2_SD,,,,TIM12_CH2,,,OTG_HS_DP,,,EVENTOUT
-PortC,PC0,,,,,,,,,,,OTG_HS_ULPI_STP,,,,,EVENTOUT
-PortC,PC1,,,,,,,,,,,,ETH_MDC,,,,EVENTOUT
-PortC,PC2,,,,,,SPI2_MISO,I2S2ext_SD,,,,OTG_HS_ULPI_DIR,ETH_MII_TXD2,,,,EVENTOUT
-PortC,PC3,,,,,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,ETH_MII_TX_CLK,,,,EVENTOUT
-PortC,PC4,,,,,,,,,,,,ETH_MII_RXD0/ETH_RMII_RXD0,,,,EVENTOUT
-PortC,PC5,,,,,,,,,,,,ETH_MII_RXD1/ETH_RMII_RXD1,,,,EVENTOUT
+PortC,PC0,,,,,,,,,,,OTG_HS_ULPI_STP,,,,,EVENTOUT,ADC123_IN10
+PortC,PC1,,,,,,,,,,,,ETH_MDC,,,,EVENTOUT,ADC123_IN11
+PortC,PC2,,,,,,SPI2_MISO,I2S2ext_SD,,,,OTG_HS_ULPI_DIR,ETH_MII_TXD2,,,,EVENTOUT,ADC123_IN12
+PortC,PC3,,,,,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,ETH_MII_TX_CLK,,,,EVENTOUT,ADC123_IN13
+PortC,PC4,,,,,,,,,,,,ETH_MII_RXD0/ETH_RMII_RXD0,,,,EVENTOUT,ADC123_IN14
+PortC,PC5,,,,,,,,,,,,ETH_MII_RXD1/ETH_RMII_RXD1,,,,EVENTOUT,ADC123_IN15
 PortC,PC6,,,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,,USART6_TX,,,,SDIO_D6,DCMI_D0,,EVENTOUT
 PortC,PC7,,,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,,USART6_RX,,,,SDIO_D7,DCMI_D1,,EVENTOUT
 PortC,PC8,,,TIM3_CH3,TIM8_CH3,,,,,USART6_CK,,,,SDIO_D0,DCMI_D2,,EVENTOUT
@@ -83,14 +83,14 @@ PortE,PE15,,TIM1_BKIN,,,,,,,,,,,FSMC_D12,,,EVENTOUT
 PortF,PF0,,,,,I2C2_SDA,,,,,,,,FSMC_A0,,,EVENTOUT
 PortF,PF1,,,,,I2C2_SCL,,,,,,,,FSMC_A1,,,EVENTOUT
 PortF,PF2,,,,,I2C2_SMBA,,,,,,,,FSMC_A2,,,EVENTOUT
-PortF,PF3,,,,,,,,,,,,,FSMC_A3,,,EVENTOUT
-PortF,PF4,,,,,,,,,,,,,FSMC_A4,,,EVENTOUT
-PortF,PF5,,,,,,,,,,,,,FSMC_A5,,,EVENTOUT
-PortF,PF6,,,,TIM10_CH1,,,,,,,,,FSMC_NIORD,,,EVENTOUT
-PortF,PF7,,,,TIM11_CH1,,,,,,,,,FSMC_NREG,,,EVENTOUT
-PortF,PF8,,,,,,,,,,TIM13_CH1,,,FSMC_NIOWR,,,EVENTOUT
-PortF,PF9,,,,,,,,,,TIM14_CH1,,,FSMC_CD,,,EVENTOUT
-PortF,PF10,,,,,,,,,,,,,FSMC_INTR,,,EVENTOUT
+PortF,PF3,,,,,,,,,,,,,FSMC_A3,,,EVENTOUT,ADC3_IN9
+PortF,PF4,,,,,,,,,,,,,FSMC_A4,,,EVENTOUT,ADC3_IN14
+PortF,PF5,,,,,,,,,,,,,FSMC_A5,,,EVENTOUT,ADC3_IN15
+PortF,PF6,,,,TIM10_CH1,,,,,,,,,FSMC_NIORD,,,EVENTOUT,ADC3_IN4
+PortF,PF7,,,,TIM11_CH1,,,,,,,,,FSMC_NREG,,,EVENTOUT,ADC3_IN5
+PortF,PF8,,,,,,,,,,TIM13_CH1,,,FSMC_NIOWR,,,EVENTOUT,ADC3_IN6
+PortF,PF9,,,,,,,,,,TIM14_CH1,,,FSMC_CD,,,EVENTOUT,ADC3_IN7
+PortF,PF10,,,,,,,,,,,,,FSMC_INTR,,,EVENTOUT,ADC3_IN8
 PortF,PF11,,,,,,,,,,,,,,DCMI_D12,,EVENTOUT
 PortF,PF12,,,,,,,,,,,,,FSMC_A6,,,EVENTOUT
 PortF,PF13,,,,,,,,,,,,,FSMC_A7,,,EVENTOUT
diff --git a/stmhal/boards/stm32f4xx-prefix.c b/stmhal/boards/stm32f4xx-prefix.c
index af3ed325c..989b8f004 100644
--- a/stmhal/boards/stm32f4xx-prefix.c
+++ b/stmhal/boards/stm32f4xx-prefix.c
@@ -21,7 +21,7 @@
     .af_fn = (af_ptr) \
 }
 
-#define PIN(p_port, p_pin, p_num_af, p_af) \
+#define PIN(p_port, p_pin, p_num_af, p_af, p_adc_num, p_adc_channel) \
 { \
     { &pin_obj_type }, \
     .name = #p_port #p_pin, \
@@ -31,4 +31,6 @@
     .pin_mask = (1 << ((p_pin) & 0x0f)), \
     .gpio = GPIO ## p_port, \
     .af = p_af, \
+    .adc_num = p_adc_num, \
+    .adc_channel = p_adc_channel, \
 }