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authorAndrew Leech2018-12-12 16:50:55 +1100
committerDamien George2019-03-08 22:58:42 +1100
commit89ff506513d52c0c415b2cf45335d60cefac527d (patch)
tree6929b54bd0f73994ccfdb09523186b7e6b40cda6 /ports
parent2e516074daee76fb3e0710a893a0f40532bb3252 (diff)
py: Update and rework build system for including external C modules.
How to use this feature is documented in docs/develop/cmodules.rst.
Diffstat (limited to 'ports')
-rw-r--r--ports/stm32/Makefile2
1 files changed, 1 insertions, 1 deletions
diff --git a/ports/stm32/Makefile b/ports/stm32/Makefile
index 4fddc6c7d..b4c7a15c1 100644
--- a/ports/stm32/Makefile
+++ b/ports/stm32/Makefile
@@ -494,7 +494,7 @@ $(BUILD)/firmware.hex: $(BUILD)/firmware.elf
$(BUILD)/firmware.elf: $(OBJ)
$(ECHO) "LINK $@"
- $(Q)$(LD) $(LDFLAGS) -o $@ $^ $(LIBS)
+ $(Q)$(LD) $(LDFLAGS) -o $@ $^ $(LDFLAGS_MOD) $(LIBS)
$(Q)$(SIZE) $@
PLLVALUES = boards/pllvalues.py