diff options
| author | Chris Mason | 2019-09-27 14:27:51 +1000 |
|---|---|---|
| committer | Damien George | 2019-10-04 21:39:17 +1000 |
| commit | 0096041c9912d34a6227f647c264325b178c0384 (patch) | |
| tree | 62204a4f1fb3bb51522d7a5e7320901658fb47e7 /ports/stm32/machine_adc.c | |
| parent | a09fd0475840ae6a24995ab7ab7955c88289817a (diff) | |
stm32/{adc,machine_adc}: Change ADC clock and sampling time for F0 MCUs.
STM32F0 has PCLK=48MHz and maximum ADC clock is 14MHz so use PCLK/4=12MHz
to stay within spec of the ADC peripheral. In pyb.ADC set common sampling
time to approx 4uS for internal and external sources. In machine.ADC
reduce sample time to approx 1uS for external source, leave internal at
maximum sampling time.
Diffstat (limited to 'ports/stm32/machine_adc.c')
| -rw-r--r-- | ports/stm32/machine_adc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/ports/stm32/machine_adc.c b/ports/stm32/machine_adc.c index 3aacae77b..22e60f043 100644 --- a/ports/stm32/machine_adc.c +++ b/ports/stm32/machine_adc.c @@ -49,7 +49,7 @@ #endif #if defined(STM32F0) -#define ADC_SAMPLETIME_DEFAULT ADC_SAMPLETIME_71CYCLES_5 +#define ADC_SAMPLETIME_DEFAULT ADC_SAMPLETIME_13CYCLES_5 #define ADC_SAMPLETIME_DEFAULT_INT ADC_SAMPLETIME_239CYCLES_5 #elif defined(STM32F4) || defined(STM32F7) #define ADC_SAMPLETIME_DEFAULT ADC_SAMPLETIME_15CYCLES @@ -126,7 +126,7 @@ STATIC void adc_config(ADC_TypeDef *adc, uint32_t bits) { // Configure clock mode #if defined(STM32F0) - adc->CFGR2 = 1 << ADC_CFGR2_CKMODE_Pos; // PCLK/2 (synchronous clock mode) + adc->CFGR2 = 2 << ADC_CFGR2_CKMODE_Pos; // PCLK/4 (synchronous clock mode) #elif defined(STM32F4) || defined(STM32F7) || defined(STM32L4) ADCx_COMMON->CCR = 0; // ADCPR=PCLK/2 #elif defined(STM32H7) |