stm32/rfcore: Update rfcore.c to match how ST examples work.

- Split tables and buffers into SRAM2A/2B.
- Use structs rather than word offsets to access tables.
- Use FLASH_IPCCDBA register value rather than option bytes directly.

1 files changed, 12 insertions, 1 deletions

diff --git a/ports/stm32/boards/stm32wb55xg.ld b/ports/stm32/boards/stm32wb55xg.ld
index dbeccc189..c3dc5f519 100644
--- a/ports/stm32/boards/stm32wb55xg.ld
+++ b/ports/stm32/boards/stm32wb55xg.ld
@@ -9,7 +9,8 @@ MEMORY
     FLASH_APP (rx)  : ORIGIN = 0x08004000, LENGTH = 496K /* sectors 4-127 */
     FLASH_FS (r)    : ORIGIN = 0x08080000, LENGTH = 256K /* sectors 128-191 */
     RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 192K /* SRAM1 */
-    RAM2A (xrw)     : ORIGIN = 0x20030020, LENGTH = 8K /* SRAM2A */
+    RAM2A (xrw)     : ORIGIN = 0x20030000, LENGTH = 10K  /* SRAM2A */
+    RAM2B (xrw)     : ORIGIN = 0x20038000, LENGTH = 10K  /* SRAM2B */
 }
 
 /* produce a link error if there is not this amount of RAM for these sections */
@@ -36,10 +37,20 @@ _flash_fs_end   = ORIGIN(FLASH_FS) + LENGTH(FLASH_FS);
 
 SECTIONS
 {
+    /* Put all IPCC tables into SRAM2A. */
     .ram2a_bss :
     {
         . = ALIGN(4);
+        . = . + 64; /* Leave room for the mb_ref_table_t (assuming IPCCDBA==0). */
         *rfcore.o(.bss.ipcc_mem_*)
         . = ALIGN(4);
     } >RAM2A
+
+    /* Put all IPCC buffers into SRAM2B. */
+    .ram2b_bss :
+    {
+        . = ALIGN(4);
+        *rfcore.o(.bss.ipcc_membuf_*)
+        . = ALIGN(4);
+    } >RAM2B
 }