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authorPaul Sokolovsky2015-10-24 02:26:10 +0300
committerPaul Sokolovsky2015-10-24 15:46:53 +0300
commit0dbd928ceefed09d65276211c70d0137b4734011 (patch)
tree27ae07b46c07da5185d3023b2e788bb102915f54 /bare-arm/Makefile
parent9a334d41e3c20dfde053cd95b9f80c384c51c2a9 (diff)
Makefiles: Remove duplicate object files when linking.
Scenario: module1 depends on some common file from lib/, so specifies it in its SRC_MOD, and the same situation with module2, then common file from lib/ eventually ends up listed twice in $(OBJ), which leads to link errors. Make is equipped to deal with such situation easily, quoting the manual: "The value of $^ omits duplicate prerequisites, while $+ retains them and preserves their order." So, just use $^ consistently in all link targets.
Diffstat (limited to 'bare-arm/Makefile')
-rw-r--r--bare-arm/Makefile2
1 files changed, 1 insertions, 1 deletions
diff --git a/bare-arm/Makefile b/bare-arm/Makefile
index dc17eed4d..a57ccfd19 100644
--- a/bare-arm/Makefile
+++ b/bare-arm/Makefile
@@ -42,7 +42,7 @@ all: $(BUILD)/firmware.elf
$(BUILD)/firmware.elf: $(OBJ)
$(ECHO) "LINK $@"
- $(Q)$(LD) $(LDFLAGS) -o $@ $(OBJ) $(LIBS)
+ $(Q)$(LD) $(LDFLAGS) -o $@ $^ $(LIBS)
$(Q)$(SIZE) $@
include ../py/mkrules.mk