stm32: Update LCD and network drivers to work with new SPI API.

3 files changed, 23 insertions, 22 deletions

diff --git a/ports/stm32/lcd.c b/ports/stm32/lcd.c
index 488df1699..62a95c070 100644
--- a/ports/stm32/lcd.c
+++ b/ports/stm32/lcd.c
@@ -89,7 +89,7 @@ typedef struct _pyb_lcd_obj_t {
     mp_obj_base_t base;
 
     // hardware control for the LCD
-    SPI_HandleTypeDef *spi;
+    const spi_t *spi;
     const pin_obj_t *pin_cs1;
     const pin_obj_t *pin_rst;
     const pin_obj_t *pin_a0;
@@ -119,7 +119,7 @@ STATIC void lcd_out(pyb_lcd_obj_t *lcd, int instr_data, uint8_t i) {
         mp_hal_pin_high(lcd->pin_a0); // A0=1; select data reg
     }
     lcd_delay();
-    HAL_SPI_Transmit(lcd->spi, &i, 1, 1000);
+    HAL_SPI_Transmit(lcd->spi->spi, &i, 1, 1000);
     lcd_delay();
     mp_hal_pin_high(lcd->pin_cs1); // CS=1; disable
 }
@@ -207,13 +207,13 @@ STATIC mp_obj_t pyb_lcd_make_new(const mp_obj_type_t *type, size_t n_args, size_
     // configure pins
     // TODO accept an SPI object and pin objects for full customisation
     if ((lcd_id[0] | 0x20) == 'x' && lcd_id[1] == '\0') {
-        lcd->spi = &SPIHandle1;
+        lcd->spi = &spi_obj[0];
         lcd->pin_cs1 = &pyb_pin_X3;
         lcd->pin_rst = &pyb_pin_X4;
         lcd->pin_a0 = &pyb_pin_X5;
         lcd->pin_bl = &pyb_pin_X12;
     } else if ((lcd_id[0] | 0x20) == 'y' && lcd_id[1] == '\0') {
-        lcd->spi = &SPIHandle2;
+        lcd->spi = &spi_obj[1];
         lcd->pin_cs1 = &pyb_pin_Y3;
         lcd->pin_rst = &pyb_pin_Y4;
         lcd->pin_a0 = &pyb_pin_Y5;
@@ -223,13 +223,13 @@ STATIC mp_obj_t pyb_lcd_make_new(const mp_obj_type_t *type, size_t n_args, size_
     }
 
     // init the SPI bus
-    SPI_InitTypeDef *init = &lcd->spi->Init;
+    SPI_InitTypeDef *init = &lcd->spi->spi->Init;
     init->Mode = SPI_MODE_MASTER;
 
     // compute the baudrate prescaler from the desired baudrate
     // select a prescaler that yields at most the desired baudrate
     uint spi_clock;
-    if (lcd->spi->Instance == SPI1) {
+    if (lcd->spi->spi->Instance == SPI1) {
         // SPI1 is on APB2
         spi_clock = HAL_RCC_GetPCLK2Freq();
     } else {
diff --git a/ports/stm32/modnwcc3k.c b/ports/stm32/modnwcc3k.c
index 4f1af7354..52787187b 100644
--- a/ports/stm32/modnwcc3k.c
+++ b/ports/stm32/modnwcc3k.c
@@ -433,7 +433,7 @@ STATIC mp_obj_t cc3k_make_new(const mp_obj_type_t *type, size_t n_args, size_t n
 
     // set the pins to use
     SpiInit(
-        spi_get_handle(args[0]),
+        spi_from_mp_obj(args[0])->spi,
         pin_find(args[1]),
         pin_find(args[2]),
         pin_find(args[3])
diff --git a/ports/stm32/modnwwiznet5k.c b/ports/stm32/modnwwiznet5k.c
index 763137c70..2fd85531f 100644
--- a/ports/stm32/modnwwiznet5k.c
+++ b/ports/stm32/modnwwiznet5k.c
@@ -48,7 +48,7 @@
 typedef struct _wiznet5k_obj_t {
     mp_obj_base_t base;
     mp_uint_t cris_state;
-    SPI_HandleTypeDef *spi;
+    const spi_t *spi;
     const pin_obj_t *cs;
     const pin_obj_t *rst;
     uint8_t socket_used;
@@ -73,12 +73,12 @@ STATIC void wiz_cs_deselect(void) {
 }
 
 STATIC void wiz_spi_read(uint8_t *buf, uint32_t len) {
-    HAL_StatusTypeDef status = HAL_SPI_Receive(wiznet5k_obj.spi, buf, len, 5000);
+    HAL_StatusTypeDef status = HAL_SPI_Receive(wiznet5k_obj.spi->spi, buf, len, 5000);
     (void)status;
 }
 
 STATIC void wiz_spi_write(const uint8_t *buf, uint32_t len) {
-    HAL_StatusTypeDef status = HAL_SPI_Transmit(wiznet5k_obj.spi, (uint8_t*)buf, len, 5000);
+    HAL_StatusTypeDef status = HAL_SPI_Transmit(wiznet5k_obj.spi->spi, (uint8_t*)buf, len, 5000);
     (void)status;
 }
 
@@ -345,23 +345,24 @@ STATIC mp_obj_t wiznet5k_make_new(const mp_obj_type_t *type, size_t n_args, size
     // init the wiznet5k object
     wiznet5k_obj.base.type = (mp_obj_type_t*)&mod_network_nic_type_wiznet5k;
     wiznet5k_obj.cris_state = 0;
-    wiznet5k_obj.spi = spi_get_handle(args[0]);
+    wiznet5k_obj.spi = spi_from_mp_obj(args[0]);
     wiznet5k_obj.cs = pin_find(args[1]);
     wiznet5k_obj.rst = pin_find(args[2]);
     wiznet5k_obj.socket_used = 0;
 
     /*!< SPI configuration */
-    wiznet5k_obj.spi->Init.Mode = SPI_MODE_MASTER;
-    wiznet5k_obj.spi->Init.Direction = SPI_DIRECTION_2LINES;
-    wiznet5k_obj.spi->Init.DataSize = SPI_DATASIZE_8BIT;
-    wiznet5k_obj.spi->Init.CLKPolarity = SPI_POLARITY_LOW; // clock is low when idle
-    wiznet5k_obj.spi->Init.CLKPhase = SPI_PHASE_1EDGE; // data latched on first edge, which is rising edge for low-idle
-    wiznet5k_obj.spi->Init.NSS = SPI_NSS_SOFT;
-    wiznet5k_obj.spi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; // clock freq = f_PCLK / this_prescale_value; Wiz820i can do up to 80MHz
-    wiznet5k_obj.spi->Init.FirstBit = SPI_FIRSTBIT_MSB;
-    wiznet5k_obj.spi->Init.TIMode = SPI_TIMODE_DISABLED;
-    wiznet5k_obj.spi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
-    wiznet5k_obj.spi->Init.CRCPolynomial = 7; // unused
+    SPI_InitTypeDef *init = &wiznet5k_obj.spi->spi->Init;
+    init->Mode = SPI_MODE_MASTER;
+    init->Direction = SPI_DIRECTION_2LINES;
+    init->DataSize = SPI_DATASIZE_8BIT;
+    init->CLKPolarity = SPI_POLARITY_LOW; // clock is low when idle
+    init->CLKPhase = SPI_PHASE_1EDGE; // data latched on first edge, which is rising edge for low-idle
+    init->NSS = SPI_NSS_SOFT;
+    init->BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; // clock freq = f_PCLK / this_prescale_value; Wiz820i can do up to 80MHz
+    init->FirstBit = SPI_FIRSTBIT_MSB;
+    init->TIMode = SPI_TIMODE_DISABLED;
+    init->CRCCalculation = SPI_CRCCALCULATION_DISABLED;
+    init->CRCPolynomial = 7; // unused
     spi_init(wiznet5k_obj.spi, false);
 
     mp_hal_pin_output(wiznet5k_obj.cs);