diff options
| author | Damien George | 2019-02-22 22:27:48 +1100 |
|---|---|---|
| committer | Damien George | 2019-02-26 23:32:19 +1100 |
| commit | ed0a5306140014b87711140aa8c6e2d229a4e46e (patch) | |
| tree | a2f6196ebf0c6ed8f83972efda60ba4d92217409 | |
| parent | b3513f54d344b431c2975b2ece992ee2b6a5a7d6 (diff) | |
stm32/boards/STM32F769DISC: Enable lwIP and Ethernet peripheral.
| -rw-r--r-- | ports/stm32/boards/STM32F769DISC/mpconfigboard.h | 13 | ||||
| -rw-r--r-- | ports/stm32/boards/STM32F769DISC/pins.csv | 9 |
2 files changed, 22 insertions, 0 deletions
diff --git a/ports/stm32/boards/STM32F769DISC/mpconfigboard.h b/ports/stm32/boards/STM32F769DISC/mpconfigboard.h index 4f41a81f9..fac7c98fd 100644 --- a/ports/stm32/boards/STM32F769DISC/mpconfigboard.h +++ b/ports/stm32/boards/STM32F769DISC/mpconfigboard.h @@ -5,6 +5,8 @@ #define MICROPY_HW_BOARD_NAME "F769DISC" #define MICROPY_HW_MCU_NAME "STM32F769" +#define MICROPY_PY_LWIP (1) + #define MICROPY_HW_HAS_SWITCH (1) #define MICROPY_HW_HAS_FLASH (1) #define MICROPY_HW_HAS_SDCARD (1) @@ -76,6 +78,17 @@ // USB config (CN15 - USB OTG HS with external PHY) #define MICROPY_HW_USB_HS (1) +// Ethernet via RMII +#define MICROPY_HW_ETH_MDC (pin_C1) +#define MICROPY_HW_ETH_MDIO (pin_A2) +#define MICROPY_HW_ETH_RMII_REF_CLK (pin_A1) +#define MICROPY_HW_ETH_RMII_CRS_DV (pin_A7) +#define MICROPY_HW_ETH_RMII_RXD0 (pin_C4) +#define MICROPY_HW_ETH_RMII_RXD1 (pin_C5) +#define MICROPY_HW_ETH_RMII_TX_EN (pin_G11) +#define MICROPY_HW_ETH_RMII_TXD0 (pin_G13) +#define MICROPY_HW_ETH_RMII_TXD1 (pin_G14) + #if 0 // Optional SDRAM configuration; requires SYSCLK <= 200MHz #define MICROPY_HW_SDRAM_SIZE (128 * 1024 * 1024 / 8) // 128 Mbit diff --git a/ports/stm32/boards/STM32F769DISC/pins.csv b/ports/stm32/boards/STM32F769DISC/pins.csv index f587d44c1..2dcc37441 100644 --- a/ports/stm32/boards/STM32F769DISC/pins.csv +++ b/ports/stm32/boards/STM32F769DISC/pins.csv @@ -69,6 +69,15 @@ UART5_TX,PC12 UART5_RX,PD2 CAN2_TX,PB13 CAN2_RX,PB12 +ETH_REF_CLK,PA1 +ETH_MDIO,PA2 +ETH_CRS_DV,PA7 +ETH_MDC,PC1 +ETH_RXD0,PC4 +ETH_RXD1,PC5 +ETH_TX_EN,PG11 +ETH_TXD0,PG13 +ETH_TXD1,PG14 FMC_SDCKE0,PH2 FMC_SDNE0,PH3 FMC_SDCLK,PG8 |