diff options
| author | Jim Mussared | 2019-09-10 21:31:53 +1000 |
|---|---|---|
| committer | Damien George | 2019-09-10 23:13:52 +1000 |
| commit | c8c37ca4076f72b79d5ec65c22a3e3bc0c71f583 (patch) | |
| tree | 330ee371a73c30358d13cbfd38f89ace8372acc5 | |
| parent | bd1d27f00f43bb44fca806cd0c53fa7196a1ea04 (diff) | |
stm32/boards/STM32F769DISC: Fix number of SDRAM row bits.
According to the schematic, the SDRAM part on this board is a
MT48LC4M32B2B5-6A, with "Row addressing 4K A[11:0]" (per datasheet). This
commit updates mpconfigboard.h from 13 to 12 to match.
| -rw-r--r-- | ports/stm32/boards/STM32F769DISC/mpconfigboard.h | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/ports/stm32/boards/STM32F769DISC/mpconfigboard.h b/ports/stm32/boards/STM32F769DISC/mpconfigboard.h index 9a700d8e4..a34b58e1b 100644 --- a/ports/stm32/boards/STM32F769DISC/mpconfigboard.h +++ b/ports/stm32/boards/STM32F769DISC/mpconfigboard.h @@ -100,7 +100,14 @@ void board_early_init(void); #define MICROPY_HW_ETH_RMII_TXD1 (pin_G14) #if 0 -// Optional SDRAM configuration; requires SYSCLK <= 200MHz +// Optional SDRAM configuration. + +// Note: This requires SYSCLK <= 200MHz. 192MHz example below: +// #define MICROPY_HW_CLK_PLLM (25) +// #define MICROPY_HW_CLK_PLLN (384) +// #define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV2) +// #define MICROPY_HW_CLK_PLLQ (8) + #define MICROPY_HW_SDRAM_SIZE (128 * 1024 * 1024 / 8) // 128 Mbit #define MICROPY_HW_SDRAM_STARTUP_TEST (0) #define MICROPY_HEAP_START sdram_start() @@ -119,7 +126,7 @@ void board_early_init(void); #define MICROPY_HW_SDRAM_BURST_LENGTH 1 #define MICROPY_HW_SDRAM_CAS_LATENCY 2 #define MICROPY_HW_SDRAM_COLUMN_BITS_NUM 8 -#define MICROPY_HW_SDRAM_ROW_BITS_NUM 13 +#define MICROPY_HW_SDRAM_ROW_BITS_NUM 12 #define MICROPY_HW_SDRAM_MEM_BUS_WIDTH 32 #define MICROPY_HW_SDRAM_INTERN_BANKS_NUM 4 #define MICROPY_HW_SDRAM_CLOCK_PERIOD 2 |