stm32/powerctrl: Move F0's SystemClock_Config to powerctrlboot.c.

2 files changed, 50 insertions, 48 deletions

diff --git a/ports/stm32/powerctrlboot.c b/ports/stm32/powerctrlboot.c
index 66beff27c..527118ba8 100644
--- a/ports/stm32/powerctrlboot.c
+++ b/ports/stm32/powerctrlboot.c
@@ -27,7 +27,56 @@
 #include "py/mphal.h"
 #include "powerctrl.h"
 
-#if defined(STM32L0)
+#if defined(STM32F0)
+
+void SystemClock_Config(void) {
+    // Enable power control peripheral
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    // Set flash latency to 1 because SYSCLK > 24MHz
+    FLASH->ACR = (FLASH->ACR & ~0x7) | 0x1;
+
+    #if MICROPY_HW_CLK_USE_HSI48
+    // Use the 48MHz internal oscillator
+
+    RCC->CR2 |= RCC_CR2_HSI48ON;
+    while ((RCC->CR2 & RCC_CR2_HSI48RDY) == 0) {
+    }
+    const uint32_t sysclk_src = 3;
+
+    #else
+    // Use HSE and the PLL to get a 48MHz SYSCLK
+
+    #if MICROPY_HW_CLK_USE_BYPASS
+    RCC->CR |= RCC_CR_HSEBYP;
+    #endif
+    RCC->CR |= RCC_CR_HSEON;
+    while ((RCC->CR & RCC_CR_HSERDY) == 0) {
+        // Wait for HSE to be ready
+    }
+    RCC->CFGR = ((48000000 / HSE_VALUE) - 2) << RCC_CFGR_PLLMUL_Pos | 2 << RCC_CFGR_PLLSRC_Pos;
+    RCC->CFGR2 = 0; // Input clock not divided
+    RCC->CR |= RCC_CR_PLLON; // Turn PLL on
+    while ((RCC->CR & RCC_CR_PLLRDY) == 0) {
+        // Wait for PLL to lock
+    }
+    const uint32_t sysclk_src = 2;
+
+    #endif
+
+    // Select SYSCLK source
+    RCC->CFGR |= sysclk_src << RCC_CFGR_SW_Pos;
+    while (((RCC->CFGR >> RCC_CFGR_SWS_Pos) & 0x3) != sysclk_src) {
+        // Wait for SYSCLK source to change
+    }
+
+    SystemCoreClockUpdate();
+
+    HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000);
+    HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
+}
+
+#elif defined(STM32L0)
 
 void SystemClock_Config(void) {
     // Enable power control peripheral
diff --git a/ports/stm32/system_stm32f0.c b/ports/stm32/system_stm32f0.c
index c3c675c74..4f561145c 100644
--- a/ports/stm32/system_stm32f0.c
+++ b/ports/stm32/system_stm32f0.c
@@ -128,53 +128,6 @@ void SystemInit(void) {
     SCB->CCR |= SCB_CCR_STKALIGN_Msk;
 }
 
-void SystemClock_Config(void) {
-    // Enable power control peripheral
-    __HAL_RCC_PWR_CLK_ENABLE();
-
-    // Set flash latency to 1 because SYSCLK > 24MHz
-    FLASH->ACR = (FLASH->ACR & ~0x7) | 0x1;
-
-    #if MICROPY_HW_CLK_USE_HSI48
-    // Use the 48MHz internal oscillator
-
-    RCC->CR2 |= RCC_CR2_HSI48ON;
-    while ((RCC->CR2 & RCC_CR2_HSI48RDY) == 0) {
-    }
-    const uint32_t sysclk_src = 3;
-
-    #else
-    // Use HSE and the PLL to get a 48MHz SYSCLK
-
-    #if MICROPY_HW_CLK_USE_BYPASS
-    RCC->CR |= RCC_CR_HSEBYP;
-    #endif
-    RCC->CR |= RCC_CR_HSEON;
-    while ((RCC->CR & RCC_CR_HSERDY) == 0) {
-        // Wait for HSE to be ready
-    }
-    RCC->CFGR = ((48000000 / HSE_VALUE) - 2) << RCC_CFGR_PLLMUL_Pos | 2 << RCC_CFGR_PLLSRC_Pos;
-    RCC->CFGR2 = 0; // Input clock not divided
-    RCC->CR |= RCC_CR_PLLON; // Turn PLL on
-    while ((RCC->CR & RCC_CR_PLLRDY) == 0) {
-        // Wait for PLL to lock
-    }
-    const uint32_t sysclk_src = 2;
-
-    #endif
-
-    // Select SYSCLK source
-    RCC->CFGR |= sysclk_src << RCC_CFGR_SW_Pos;
-    while (((RCC->CFGR >> RCC_CFGR_SWS_Pos) & 0x3) != sysclk_src) {
-        // Wait for SYSCLK source to change
-    }
-
-    SystemCoreClockUpdate();
-
-    HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000);
-    HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
-}
-
 void SystemCoreClockUpdate(void) {
     // Get SYSCLK source
     uint32_t tmp = RCC->CFGR & RCC_CFGR_SWS;