diff options
| author | roland | 2018-10-24 22:52:36 +0200 |
|---|---|---|
| committer | Damien George | 2018-11-01 13:25:47 +1100 |
| commit | 30ed2b3cabd4fe3cc8e0b865846a05d957937a50 (patch) | |
| tree | 323e08e557437353a8cccd69c1414b7e47d99c11 | |
| parent | 06643a0df4e85cbdf18549440db19dc21fccbf76 (diff) | |
stm32/system_stm32: Introduce configuration defines for PLL3 settings.
A board must be able to set the PLL3 values based on the HSE that it uses.
| -rw-r--r-- | ports/stm32/boards/NUCLEO_H743ZI/mpconfigboard.h | 7 | ||||
| -rw-r--r-- | ports/stm32/system_stm32.c | 10 |
2 files changed, 12 insertions, 5 deletions
diff --git a/ports/stm32/boards/NUCLEO_H743ZI/mpconfigboard.h b/ports/stm32/boards/NUCLEO_H743ZI/mpconfigboard.h index 117e7f3f6..05645633f 100644 --- a/ports/stm32/boards/NUCLEO_H743ZI/mpconfigboard.h +++ b/ports/stm32/boards/NUCLEO_H743ZI/mpconfigboard.h @@ -20,6 +20,13 @@ void NUCLEO_H743ZI_board_early_init(void); #define MICROPY_HW_CLK_PLLQ (4) #define MICROPY_HW_CLK_PLLR (2) +// The USB clock is set using PLL3 +#define MICROPY_HW_CLK_PLL3M (4) +#define MICROPY_HW_CLK_PLL3N (120) +#define MICROPY_HW_CLK_PLL3P (2) +#define MICROPY_HW_CLK_PLL3Q (5) +#define MICROPY_HW_CLK_PLL3R (2) + // 4 wait states #define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_4 diff --git a/ports/stm32/system_stm32.c b/ports/stm32/system_stm32.c index b57b8e10f..e0e27cef0 100644 --- a/ports/stm32/system_stm32.c +++ b/ports/stm32/system_stm32.c @@ -517,11 +517,11 @@ void SystemClock_Config(void) /* PLL3 for USB Clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3; - PeriphClkInitStruct.PLL3.PLL3M = 4; - PeriphClkInitStruct.PLL3.PLL3N = 120; - PeriphClkInitStruct.PLL3.PLL3P = 2; - PeriphClkInitStruct.PLL3.PLL3Q = 5; - PeriphClkInitStruct.PLL3.PLL3R = 2; + PeriphClkInitStruct.PLL3.PLL3M = MICROPY_HW_CLK_PLL3M; + PeriphClkInitStruct.PLL3.PLL3N = MICROPY_HW_CLK_PLL3N; + PeriphClkInitStruct.PLL3.PLL3P = MICROPY_HW_CLK_PLL3P; + PeriphClkInitStruct.PLL3.PLL3Q = MICROPY_HW_CLK_PLL3Q; + PeriphClkInitStruct.PLL3.PLL3R = MICROPY_HW_CLK_PLL3R; PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_1; PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE; PeriphClkInitStruct.PLL3.PLL3FRACN = 0; |