| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2021-08-27 | Removed older ALU from Chisel fileHEADmaster | Aditya Naik | |
| This was not needed | |||
| 2021-08-27 | Initial; working SAIL RISC-V regs | Aditya Naik | |
| The register definition along with read/write functions for registers are lowered to Coq. The FIRRTL annotation does not work as expected. | |||
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index : firrtl-coq | |
| Formal verification of FIRRTL components using Coq definitions generated from SAIL RISC-V specs | Aditya N. Naik |
| summaryrefslogtreecommitdiff |
path: root/components.scala