blob: d2e42fa9abb48bb7bb109224873830260ed93c78 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
|
// See LICENSE for license details.
package chiselTests
import Chisel._
import org.scalatest._
import org.scalatest.prop._
import Chisel.testers.BasicTester
class Coord extends Bundle {
val x = UInt(width = 32)
val y = UInt(width = 32)
}
class BundleWire(n: Int) extends Module {
val io = new Bundle {
val in = (new Coord).asInput
val outs = Vec(n, new Coord).asOutput
}
val coords = Wire(Vec(n, new Coord))
for (i <- 0 until n) {
coords(i) := io.in
io.outs(i) := coords(i)
}
}
class BundleWireTester(n: Int, x: Int, y: Int) extends BasicTester {
val dut = Module(new BundleWire(n))
dut.io.in.x := UInt(x)
dut.io.in.y := UInt(y)
for (elt <- dut.io.outs) {
assert(elt.x === UInt(x))
assert(elt.y === UInt(y))
}
stop()
}
class BundleWireSpec extends ChiselPropSpec {
property("All vec elems should match the inputs") {
forAll(vecSizes, safeUInts, safeUInts) { (n: Int, x: Int, y: Int) =>
assertTesterPasses{ new BundleWireTester(n, x, y) }
}
}
}
|