blob: 94c340c418fd210e303331039f8973ee7df42967 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
|
// See LICENSE for license details.
/** LFSRs in all shapes and sizes.
*/
package chisel3.util
import chisel3._
import chisel3.internal.naming.chiselName // can't use chisel3_ version because of compile order
//import chisel3.core.ExplicitCompileOptions.Strict
// scalastyle:off magic.number
object LFSR16 {
/** Generates a 16-bit linear feedback shift register, returning the register contents.
* May be useful for generating a pseudorandom sequence.
*
* @param increment optional control to gate when the LFSR updates.
*/
@chiselName
def apply(increment: Bool = true.B): UInt = {
val width = 16
val lfsr = Reg(init=1.U(width.W))
when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) }
lfsr
}
}
// scalastyle:on magic.number
|
