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#+STARTUP: indent content
#+TODO: TODO STALLED WONTFIX | DONE
* [2024-01-10 Wed] commit 7a3a5a07e
** log
- As of today I have a working `connectTypes` method which uses
user-supplied type arithmetic in the `TypeArithmetic` object to
resolve connected types.
- Motivation for connectTypes was to replicate the functionality of
diplomacy when it does ":="
- Chatting with Adam about this, we noted the difference in philosophy
between `connectTypes` and diplomatic `:=` connection.
** `connectTypes` vs diplomatic `:=`
- Diplomatic connections serve to "note down" the connection to be
made with `makeIOs`. These connections are made after the second
stage of diplomacy finishes and the types are resolved. So there's a
sequence of events with `:=`
- `connectTypes` resolve types /and/ make the IO connections at the
same time.
* [2024-02-14 Wed] Wokring AbstractInterface arithmetic
** log
- Add a new file AbstractModuleStandalone.scala which i copied over from scastie
- Add a new implicit generic function =abstractInterfaceConnection=
which allows perfoming computations on AbstractInterfaces. Now, the
user only needs to supply type arithmetic on =A => B => C= in order
to get =AbstractInterface[A] => AbstractInterface[B] =>
AbstractInterface[C]= to work.
- Next step will to be figure out multiple arities for =AbstractInterface=
* [2024-03-07 Thu] realization
- key realization this morning: there's a problematic muddling of two
separate things in chisel: the /content of the module body/ and
/scala-time computations/
- verilog module bodies need to be simple,
post-scala-computation-representations of what computations actually
need to be in hardware.
** consequences of this problem at sifive
- diplomacy creates multiple levels of scala-time computations while
abstracting away the module body.
- lazymodule is the scala-time computation, lazymoduleimp is the verilog body
- people need to insert shit into bodies of "modules" using InModuleBody
- interface of resulting modules is indeterminable
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