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---
layout: docs
title: "Naming Cookbook"
section: "chisel3"
---
```scala mdoc:invisible
import chisel3._
import chisel3.stage.ChiselStage
```
# Naming Cookbook
### I still have _T signals, can this be fixed?
See the next answer!
### I have so many wires with the same name, like `x`, `x_1` and `x_2`. How can I make them easier to understand?
Signals with `_T` names or names that Chisel has to uniquify
often are intermediate values generated within loops, function calls, or `when` predicates.
They can also be consumed by verification statements like `assert` or `prints`.
In these cases, the compiler plugin often can't find a good prefix for the generated
intermediate signals and can't name them at all or has to make up a unique name for them.
We recommend you manually insert calls to `prefix` to clarify these cases:
```scala mdoc:silent
import chisel3.experimental.prefix
class ExamplePrefix extends Module {
Seq.tabulate{2} {i =>
Seq.tabulate{2}{ j =>
prefix(s"loop_${i}_${j}"){
val x = WireInit((i*0x10+j).U(8.W))
dontTouch(x)
}
}
}
}
```
```scala mdoc:verilog
ChiselStage.emitVerilog(new ExamplePrefix)
```
### How can I get better names for code generated by `when` clauses?
The `prefix` API can help with code inside `when` clauses:
```scala mdoc:silent
class ExampleWhenPrefix extends Module {
val in = IO(Input(UInt(4.W)))
val out = IO(Output(UInt(4.W)))
out := DontCare
Seq.tabulate{2}{ i =>
val j = i + 1
when (in === j.U) { prefix(s"clause_${j}"){
val foo = Wire(UInt(4.W))
foo := in +& j.U(4.W)
out := foo
}}
}
}
```
```scala mdoc:verilog
ChiselStage.emitVerilog(new ExampleWhenPrefix)
```
### I still see _GEN signals, can this be fixed?
`_GEN` signals are usually generated from the FIRRTL compiler, rather than the Chisel library. We are working on
renaming these signals with more context-dependent names, but it is a work in progress. Thanks for caring!
### My module names are super unstable - I change one thing and Queue_1 becomes Queue_42. Help!
This is the infamous `Queue` instability problem. In general, these cases are best solved at the source - the module
itself! If you overwrite `desiredName` to include parameter information (see the
[explanation](../explanations/naming#set-a-module-name) for more info), then this can avoid this problem permanantly.
We've done this with some Chisel utilities with great results!
### I want to add some hardware or assertions, but each time I do all the signal names get bumped!
This is the classic "ECO" problem, and we provide descriptions in [explanation](../explanations/naming). In short,
we recommend wrapping all additional logic in a prefix scope, which enables a unique namespace. This should prevent
name collisions, which are what triggers all those annoying signal name bumps!
### I want to force a signal (or instance) name to something, how do I do that?
Use the `.suggestName` method, which is on all classes which subtype `Data`.
### How can I omit the prefix in certain parts of the code?
You can use the `noPrefix { ... }` to strip the prefix from all signals generated in that scope.
```scala mdoc
import chisel3.experimental.noPrefix
class ExampleNoPrefix extends Module {
val in = IO(Input(UInt(2.W)))
val out = IO(Output(UInt()))
val add = noPrefix { in + in + in }
out := add
}
```
```scala mdoc:verilog
ChiselStage.emitVerilog(new ExampleNoPrefix)
```
### I am still not getting the name I want. For example, inlining an instance changes my name!
In cases where a FIRRTL transform renames a signal/instance, you can use the `forcename` API:
```scala mdoc
import chisel3.util.experimental.{forceName, InlineInstance}
class WrapperExample extends Module {
val in = IO(Input(UInt(3.W)))
val out = IO(Output(UInt(3.W)))
val inst = Module(new Wrapper)
inst.in := in
out := inst.out
}
class Wrapper extends Module with InlineInstance {
val in = IO(Input(UInt(3.W)))
val out = IO(Output(UInt(3.W)))
val inst = Module(new MyLeaf)
forceName(inst, "inst")
inst.in := in
out := inst.out
}
class MyLeaf extends Module {
val in = IO(Input(UInt(3.W)))
val out = IO(Output(UInt(3.W)))
out := in
}
```
```scala mdoc:verilog
ChiselStage.emitVerilog(new WrapperExample)
```
This can be used to rename instances and non-aggregate typed signals.
|
