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// SPDX-License-Identifier: Apache-2.0
package chisel3
import chisel3.internal.firrtl.{IntervalRange, SLit, Width}
trait SIntFactory {
/** Create an SInt type with inferred width. */
def apply(): SInt = apply(Width())
/** Create a SInt type or port with fixed width. */
def apply(width: Width): SInt = new SInt(width)
/** Create a SInt with the specified range */
def apply(range: IntervalRange): SInt = {
apply(range.getWidth)
}
/** Create an SInt literal with specified width. */
protected[chisel3] def Lit(value: BigInt, width: Width): SInt = {
val lit = SLit(value, width)
val result = new SInt(lit.width)
lit.bindLitArg(result)
}
}
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