1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
|
// SPDX-License-Identifier: Apache-2.0
package chisel3.experimental
import scala.language.existentials
import chisel3.internal.{Builder, InstanceId, LegacyModule}
import chisel3.{CompileOptions, Data, RawModule}
import firrtl.Transform
import firrtl.annotations._
import firrtl.options.Unserializable
import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation}
/** Interface for Annotations in Chisel
*
* Defines a conversion to a corresponding FIRRTL Annotation
*/
trait ChiselAnnotation {
/** Conversion to FIRRTL Annotation */
def toFirrtl: Annotation
}
/** Mixin for [[ChiselAnnotation]] that instantiates an associated FIRRTL Transform when this Annotation is present
* during a run of
* [[Driver$.execute(args:Array[String],dut:()=>chisel3\.RawModule)* Driver.execute]].
* Automatic Transform instantiation is *not* supported when the Circuit and Annotations are serialized before invoking
* FIRRTL.
*/
trait RunFirrtlTransform extends ChiselAnnotation {
def transformClass: Class[_ <: Transform]
}
object annotate {
def apply(anno: ChiselAnnotation): Unit = {
Builder.annotations += anno
}
}
/** Marks that a module to be ignored in Dedup Transform in Firrtl pass
*
* @example {{{
* def fullAdder(a: UInt, b: UInt, myName: String): UInt = {
* val m = Module(new Module {
* val io = IO(new Bundle {
* val a = Input(UInt(32.W))
* val b = Input(UInt(32.W))
* val out = Output(UInt(32.W))
* })
* override def desiredName = "adder_" + myNname
* io.out := io.a + io.b
* })
* doNotDedup(m)
* m.io.a := a
* m.io.b := b
* m.io.out
* }
*
* class AdderTester extends Module
* with ConstantPropagationTest {
* val io = IO(new Bundle {
* val a = Input(UInt(32.W))
* val b = Input(UInt(32.W))
* val out = Output(Vec(2, UInt(32.W)))
* })
*
* io.out(0) := fullAdder(io.a, io.b, "mod1")
* io.out(1) := fullAdder(io.a, io.b, "mod2")
* }
* }}}
*
* @note Calling this on [[Data]] creates an annotation that Chisel emits to a separate annotations
* file. This file must be passed to FIRRTL independently of the `.fir` file. The execute methods
* in [[chisel3.Driver]] will pass the annotations to FIRRTL automatically.
*/
object doNotDedup {
/** Marks a module to be ignored in Dedup Transform in Firrtl
*
* @param module The module to be marked
* @return Unmodified signal `module`
*/
def apply[T <: RawModule](module: T)(implicit compileOptions: CompileOptions): Unit = {
annotate(new ChiselAnnotation { def toFirrtl = NoDedupAnnotation(module.toNamed) })
}
}
|
