summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2021-09-06Fix #2112, handle `?->1` caseBoyang Han
2021-09-06Test case reworkBoyang Han
2021-09-06Add a test case to demonstrate the bug found in #2112Boyang Han
2021-09-05Add Definition and Instance API (#2045)Adam Izraelevitz
This introduces a new experimental API for module instantiation that disentagles elaborating the definition (or implementation) from instantiation of a given module. This solves Chisel's longstanding reliance on "Deduplication" for generating Verilog with multiple instances of the same module. The new API resides in package chisel3.experimental.hierarchy. Please see the hierarchy ScalaDoc, documentation, and tests for examples of use. Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-08-31Fix chisel3 <> for compatibility Bundles (Take 3) (#2093)Jack Koenig
Previous incomplete fixes in #2023 and #2031. The legality of a FIRRTL connection is determined by type and flow. Chisel does not have access to true flow information. Previous fix attempts tried to use ActualDirection as a stand-in for flow, but it is incorrect in many cases. This new approach checks the flows of the lvalue and rvalues in the connect and flips the connection if either the lvalue cannot be a sink or the rvalue cannot be a source.
2021-08-26add new APIs to BitPat (#2076)Jiuyang Liu
* add Y and N to BitPat. * add ## for BitPat. * add rawString API. * use rawString in decoder * add select and slice to BitPat.
2021-08-25replace custom model checker with chiseltest formal verify command (#2075)Kevin Laeufer
* replace custom model checker with chiseltest formal verify command * integration-tests can make use of chiseltest This is a compromise solution to avoid issues with binary compatibility breaking changes in chisel3. * ci: move integration tests into separate job * run integration tests only for one scala version * ci: install espresso for integration tests * Update build.sbt Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
2021-08-23Use BufferedCustomFileEmission in CircuitSerializationAnnotationJack Koenig
2021-08-23Emit .fir lazily, overcomes JVM 2 GiB String limitJack Koenig
2021-08-23Remove chisel3's own firrtl Emitter, use firrtl SerializerJack Koenig
This will be slightly slower as it involves converting from Chisel modules to FIRRTL modules before turning them into Strings. This cost is somewhat mitigated by doing that conversion lazily such that we never materialize the entire firrtl Circuit in memory, only 1 module at a time.
2021-08-23Add multiple dimensions to VecInit fill and iterate (#2065)anniej-sifive
Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-08-21Update ChiselStage.scala (#2082)Ruige Lee
There might be some "@"?
2021-08-18Revert "remove DefRegInit, change DefReg API with option definition. ↵Jack Koenig
(#1944)" (#2080) This reverts commit ed894c61474c8bc73761a6c360ef9d14505d853b.
2021-08-17remove DefRegInit, change DefReg API with option definition. (#1944)Jiuyang Liu
* remove DefRegInit, change DefReg API with option defination. * add error message * use Option[RegInitIR]. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-08-12Add DataView (#1955)Jack Koenig
DataView is a mechanism for "viewing" Scala objects as a subtype of `Data`. Often, this is useful for viewing one subtype of `Data`, as another. One can think about a DataView as a cross between a customizable cast and an untagged union. A DataView has a Target type `T`, and a View type `V`. DataView requires that an implementation of `DataProduct` is available for Target types. DataProduct is a type class that provides a way to iterate on `Data` children of objects of implementing types. If a DataView is provided for a type T to a type V, then the function .viewAs[V] (of type T => V) is available. The object (of type T) returned by .viewAs is called a "View" and can be used as both an rvalue and an lvalue. Unlike when using an .asTypeOf cast, connecting to a "View" will connect to the associated field or fields of the underlying Target. DataView also enables .viewAsSupertype which is available for viewing Bundles as a parent Bundle type. It is similar to .viewAs but requires a prototype object of the Target type which will be cloned in order to create the returned View. .viewAsSupertype maps between the corresponding fields of the parent and child Bundle types.
2021-08-12Pass truth table to espresso using stdin instead of temp fileBoyang Han
2021-08-04Added VecInit factory methods (fill,iterate) (#2059)anniej-sifive
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-08-03Added flush capability to Queue (#2030)anniej-sifive
Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Deborah Soung <debs@sifive.com>
2021-07-28Bundles can no longer be instantiated with bound hardware (#2046)Jared Barocsi
Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-07-14Fix Cat rename signal (#2011)Leway Colin
Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-07-14Espresso Decoder (#1964)Jiuyang Liu
Co-authored-by: Haoran Yuan <sinofp@tuta.io> Co-authored-by: Boyang Han <yqszxx@gmail.com>
2021-07-09Fix chisel3 <> for Bundles that contain compatibility Bundles (Take 2) (#2031)Jack Koenig
PR #2023 fixed a composition issue for chisel3 biconnects delegating to FIRRTL partial connect when compatibility mode Bundles are elements of chisel3 Bundles. It missed an important case though that caused previously working code to break. The bug is fixed by doing the automatic flipping for compatibility mode Bundles that have "Input" as a direction in addition to those that are "Flipped".
2021-07-08Make it legal for concrete resets to drive abstract reset (#2018)Jack Koenig
This has been legal in FIRRTL since v1.2.3 (when reset inference started using a unification-style algorithm) but was never exposed in the Chisel API. Also delete the overridden connects in AsyncReset and ResetType which just duplicate logic from MonoConnect.
2021-07-08Fix chisel3 <> for Bundles that contain compatibility Bundles (#2023)Jack Koenig
BiConnect in chisel3 delegates to FIRRTL <- semantics whenever it hits a Bundle defined in `import Chisel._`. Because chisel3 <> is commutative it needs to be mindful of flippedness when emitting a FIRRTL <- (which is *not* commutative).
2021-07-08Add `isOneOf` method to `ChiselEnum` (#1966)Verneri Hirvonen
* Add @ekiwi's code as a starting point * Add test for ChiselEnum isOneOf method * Make isOneOfTester naming consistent with other testers * Add scaladoc comments for isOneOf * Add isOneOf tests that use the method that takes variable number of args * Add guide level documentation example for isOneOf
2021-07-06Make printf return BaseSim subclass so it can be named/annotated (#1992)Deborah Soung
2021-07-01Add ChiselEnum.safe factory method and avoid warningJack Koenig
Previously, ChiselEnum would warn any time a UInt is converted to an Enum. There was no way to suppress this warning. Now there is a factory method (`.safe`) that does not warn and returns (Enum, Bool) where the Bool is the result of calling .isValid on an Enum object. The regular UInt cast is also now smarter and will not warn if all bitvectors of the width of the Enum are legal states.
2021-06-30Add 7 segment display decoder test caseBoyang Han
2021-06-29Change behavior of aop.Select to not include CloneModuleAsRecordJack Koenig
Previously, CloneModuleAsRecord clones would result in the same BaseModule object coming up multiple times when using APIs like .instances, .collectDeep, and .getDeep. This was not the intended behavior and can lead to very subtle bugs.
2021-06-29Restore aop.Select behavior for CloneModuleAsRecordJack Koenig
2021-06-28Fix CloneModuleAsRecord support for .toTargetJack Koenig
2021-06-24create and extend annotatable BaseSim class for verification nodes (#1968)Deborah Soung
* prototype annotating verif constructs * switch to final class * name emissions * moving BaseSim to experimental * adding name tests * fixing quotation escapes * emitting names, but everything has a default name * only name things with provided/suggested names * name every BaseSim node * removing msg, unused imports * fixing file exist calls
2021-06-23Replace hard coded line separators with system specific onesBoyang Han
2021-06-21Bump scalatest to 3.2.9 (#1965)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-06-16getVerilog in Chisel3 (#1921)Martin Schoeberl
2021-06-16implement test for qmcJiuyang Liu
2021-06-16Add computational complexity analysisBoyang Han
2021-06-16Refactor to a more `scala` formBoyang Han
2021-06-16Merge minimized table before return as a TruthTableBoyang Han
2021-06-16implement QMC.Boyang Han
2021-06-16Apply Jack's Review Jiuyang Liu
1. `TruthTable` is final now. 2. add return type for `TruthTable` Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-06-16add documentation for DecodeTableAnnotation.Jiuyang Liu
2021-06-16Add test cases.Jiuyang Liu
2021-06-16switch to EndToEndSMTBaseSpecJiuyang Liu
2021-06-16Add minimized form of test casesBoyang Han
2021-06-16use z3 formal check minimized circuit and reference model.Jiuyang Liu
2021-06-16test decode cache.Jiuyang Liu
2021-06-16remove all timeouts by review.Jiuyang Liu
2021-06-16async decoder with 5 seconds timeout.Jiuyang Liu
2021-06-16add a simple decoder API.Jiuyang Liu
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-09 15:09:56 +0000