summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2021-07-06Make printf return BaseSim subclass so it can be named/annotated (#1992)Deborah Soung
2021-07-01Add ChiselEnum.safe factory method and avoid warningJack Koenig
Previously, ChiselEnum would warn any time a UInt is converted to an Enum. There was no way to suppress this warning. Now there is a factory method (`.safe`) that does not warn and returns (Enum, Bool) where the Bool is the result of calling .isValid on an Enum object. The regular UInt cast is also now smarter and will not warn if all bitvectors of the width of the Enum are legal states.
2021-06-30Add 7 segment display decoder test caseBoyang Han
2021-06-29Change behavior of aop.Select to not include CloneModuleAsRecordJack Koenig
Previously, CloneModuleAsRecord clones would result in the same BaseModule object coming up multiple times when using APIs like .instances, .collectDeep, and .getDeep. This was not the intended behavior and can lead to very subtle bugs.
2021-06-29Restore aop.Select behavior for CloneModuleAsRecordJack Koenig
2021-06-28Fix CloneModuleAsRecord support for .toTargetJack Koenig
2021-06-24create and extend annotatable BaseSim class for verification nodes (#1968)Deborah Soung
* prototype annotating verif constructs * switch to final class * name emissions * moving BaseSim to experimental * adding name tests * fixing quotation escapes * emitting names, but everything has a default name * only name things with provided/suggested names * name every BaseSim node * removing msg, unused imports * fixing file exist calls
2021-06-23Replace hard coded line separators with system specific onesBoyang Han
2021-06-21Bump scalatest to 3.2.9 (#1965)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-06-16getVerilog in Chisel3 (#1921)Martin Schoeberl
2021-06-16implement test for qmcJiuyang Liu
2021-06-16Add computational complexity analysisBoyang Han
2021-06-16Refactor to a more `scala` formBoyang Han
2021-06-16Merge minimized table before return as a TruthTableBoyang Han
2021-06-16implement QMC.Boyang Han
2021-06-16Apply Jack's Review Jiuyang Liu
1. `TruthTable` is final now. 2. add return type for `TruthTable` Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-06-16add documentation for DecodeTableAnnotation.Jiuyang Liu
2021-06-16Add test cases.Jiuyang Liu
2021-06-16switch to EndToEndSMTBaseSpecJiuyang Liu
2021-06-16Add minimized form of test casesBoyang Han
2021-06-16use z3 formal check minimized circuit and reference model.Jiuyang Liu
2021-06-16test decode cache.Jiuyang Liu
2021-06-16remove all timeouts by review.Jiuyang Liu
2021-06-16async decoder with 5 seconds timeout.Jiuyang Liu
2021-06-16add a simple decoder API.Jiuyang Liu
2021-06-16implement abstract Minimizer as a general API.Jiuyang Liu
2021-06-16fix for 2.13Jiuyang Liu
2021-06-16TruthTable can merge same inputs now.Jiuyang Liu
2021-06-16implement DecodeTableAnnotation for decode table caching.Jiuyang Liu
2021-06-16implement TruthTable to represent a decode table.Jiuyang Liu
2021-06-10Stop Emitting BlackBoxResourceAnno (#1954)Schuyler Eldridge
* Change HasBlackBoxResource to Resolve Resources Change HasBlackBoxResource to resolve resources immediately and emit BlackBoxInlineAnno instead of a BlackBoxResourceAnno. This removes the need for a FIRRTL compiler to grok the Java Resource API in order to handle BlackBoxResourceAnno. Emit BlackBoxInlineAnno from HasExtModuleResource instead of BlackBoxResourceAnno. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-05-25throw exception if BitPat width is 0 (#1920)Jiuyang Liu
* spot a bug when BitPat width is 0 * fix #1919 Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-20Implement PLA (#1912)Jiuyang Liu
* implement pla * implement test for pla * implement inverter matrix of PLA generator * fix for review. Co-authored-by: Boyang Han <yqszxx@gmail.com>
2021-05-20implement model checking API for chiseltest (#1910)Jiuyang Liu
* add os-lib to dependency. * implement EndToEndSMTBaseSpec * rename to SMTModelCheckingSpec * add documentation. * fix for review.
2021-05-10implement equal to BitPat. (#1867)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-09Fix ShiftRegister with 0 delay. (#1903)Jiuyang Liu
* Add test to check ShiftRegister(s) with delay is 0. This should break ShiftRegister(x, 0) since last is not exist in a empty Seq. Originally, test only test 1 to 4, which missed a potential bug from #1723. * Fix ShiftRegister with 0 delay. if ShiftRegisters is empty, java will complain: ``` java.util.NoSuchElementException scala.collection.LinearSeqOptimized.last(LinearSeqOptimized.scala:150) ``` This fix this issue and return `in` directly when ShiftRegister size is 0. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-06add ShiftRegisters to expose register inside ShiftRegister. (#1723)Jiuyang Liu
* add ShiftRegisters to expose register inside ShiftRegister. * use Seq.iter for oneline implementation.
2021-05-05Remove chisel3.stage.phases.DriverCompatibility (#1772)Schuyler Eldridge
2021-04-30add helper function to convert chirrtl to firrtl. (#1854)Jiuyang Liu
* add convert(chirrtl: cir.Circuit): fir.Circuit to convert chirrtl to firrtl. * add scaladoc. * add test. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-29Scala 2.13 support (#1751)Jack Koenig
2021-04-29verification: guard statements with module reset (#1891)Kevin Laeufer
2021-04-27Introduce VecLiterals (#1834)Chick Markley
This PR provides for support for Vec literals. They can be one of two forms Inferred: ``` Vec.Lit(0x1.U, 0x2.U) ``` or explicit: ``` Vec(2, UInt(4.W)).Lit(0 -> 0x1.U, 1 -> 0x2.U) ``` - Explicit form allows for partial, or sparse, literals. - Vec literals can be used as Register initializers - Arbitrary nesting (consistent with type constraints is allowed)
2021-04-21fixing context bug (#1874)Deborah Soung
2021-03-23Make plugin autoclonetype always on (#1826)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-03-18Add toString method to BitPat (#1819)Boyang Han
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-03-18Don't toggle top.cpp clock and reset on same cycle (#1820)Schuyler Eldridge
Change top.cpp to deassert reset one time unit before the clock asserts. This avoids a Verilator simultation issue in top.cpp where the eval() function is only called once per simultation loop. If the clock and reset are both changed and eval() is only called once, then any combinational update due to a change in reset is not visible to the sequential logic. This avoids issues where the downstream compilation utilities move synchronous reset logic outside of an always block that describes a synchronous reset flip flop. Reset now deasserts on time unit 10 and the clock ticks on time unit 11. h/t @albert-magyar Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-03-17Fix incorrect usage of emitFirrtl in test (#1817)Schuyler Eldridge
Change a test to use emitChirrtl instead of emitFirrtl. This test isn't supposed to be running the Scala FIRRTL Compiler, but the latter method causes this to happen. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-03-15allowReflectiveAutoCloneType must work outside of Builder context (#1811)Jack Koenig
2021-03-12[plugin] Disable BundleComponent by default, add option to enableJack Koenig
2021-03-12[plugin] Implement autoclonetype in the compiler pluginJack Koenig
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 14:09:08 +0000