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2022-05-27Make ExtModule port naming consistent with Module (#2548) (#2549)mergify[bot]
ExtModule now uses the same namePorts implementation as regular Modules. Previously, ExtModules only allowed port naming via runtime reflection. This meant that .suggestName and other naming APIs do not work. It also breaks FlatIO for ExtModule which is a potential replacement API for BlackBox's special `val io` handling. (cherry picked from commit 83cccfb782d9141bf2c843246c2a525c62392924) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-24Support Vecs of empty Bundles (#2543) (#2545)mergify[bot]
(cherry picked from commit a1e3a6b5324997864168111bee8c02a60abb0acc) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-19Support := views to DontCare (#2536) (#2539)mergify[bot]
(cherry picked from commit 77a6c93592d5766d66f199720fc6d69478005091) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-14Deprecate named arguments for methods moving to macros in 3.6 (#2530)Jack Koenig
These methods will start using def macros and since def macros do not supported named arguments this will be a source-incompatible change. This deprecation will warn users that they need to remove any uses of named arguments on these methods.
2022-05-12Support separately elaborating definition and instance in ChiselStage ↵mergify[bot]
(backport #2512) (#2520) * Support separately elaborating definition and instance in ChiselStage (#2512) (cherry picked from commit a0aa4d1550e3fbde199a98529cffeb176fb4bed8) # Conflicts: # core/src/main/scala/chisel3/experimental/hierarchy/Definition.scala # core/src/main/scala/chisel3/experimental/hierarchy/Instance.scala # core/src/main/scala/chisel3/internal/Builder.scala * fixing imports (#2522) Co-authored-by: Deborah Soung <debs@sifive.com>
2022-04-25Fix error message for BlackBox without val io <: Record (#2504) (#2505)mergify[bot]
(cherry picked from commit f9aee1f72744abc6ee13aafc4d1a51a2783cbab8) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-04-20Generate a balanced tree with reduceTree (#2318) (#2499)mergify[bot]
The difference in logic depth for various paths now has a maximum of 1. Also make treeReduce order the same for 2.12 and 2.13 .grouped(_) returns an Iterator .toSeq on an Iterator returns a Stream in 2.12 and a List in 2.13 This can lead to changes in order when bumping from 2.12 to 2.13 that can be avoided by simply using an eager collection explicitly. Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 6975f77f3325dec46c613552eac663c29011a67c) Co-authored-by: Martin Schoeberl <martin@jopdesign.com>
2022-04-19Allow creating memories without an implicit clock (#2494) (#2495)mergify[bot]
Fixes #2470 (cherry picked from commit 44165a259bb16733a41798edca6b554b13f1d54a) Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>
2022-04-15Enable Clock Invalidation (#2485) (#2487)mergify[bot]
Loosen restrictions on clocks to enable them to be connected to DontCare, i.e., be invalidated. Co-authored-by: Jack Koenig <koenig@sifive.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 5d8a0c8e406376f7ceda91273fb0fa7a646865aa) Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2022-04-12Enhance views to [sometimes] support dynamic indexing and implement FlatIO ↵mergify[bot]
(backport #2476) (#2479) * Capture 1:1 mappings of Aggregates inside of views This is implemented by including any corresponding Aggregates from the DataView.mapping in the AggregateViewBinding.childMap (which is now of type Map[Data, Data]). This enables dynamically indexing Vecs that are themselves elements of larger Aggregates in views when the corresponding element of the view is a Vec of the same type. It also increases the number of cases where a single Target can represent part of a view. (cherry picked from commit 1f6b1ca14ccf86918065073c3f6f3626dd83a68e) * Add FlatIO API for creating ports from Bundles without a prefix (cherry picked from commit 772a3a1fe3b9372b7c2d7cd2d424b2adcd633cdb) * [docs] Add FlatIO to the general cookbook (cherry picked from commit b4159641350f238f0f899b69954142ce8ee11544) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-04-01Prevent FIRRTL bulk connects on BlackBox Bundles. (#2468) (#2469)mergify[bot]
(cherry picked from commit 4da1e89f3a0b79adcb39ea5defb393ed6c00fa2f) Co-authored-by: fzi-hielscher <47524191+fzi-hielscher@users.noreply.github.com>
2022-03-25rm unused/deprecated BlackBoxResourceAnno import (#2458) (#2460)mergify[bot]
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> (cherry picked from commit 2c2d72ceaa494b6acc351ff4300dbb40d4a7d863) Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2022-03-10Emit FIRRTL bulkconnects whenever possible (#2381) (#2440)mergify[bot]
Chisel <> semantics differ somewhat from FIRRTL <= semantics, so we only emit <= when it would be legal. Otherwise we continue the old behavior of emitting a connection for every leaf-level Element. Co-authored-by: Deborah Soung <debs@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 3553a1583403824718923a6cc530cec3b38f5704) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-03-09Support BlackBoxes in D/I (#2438) (#2442)mergify[bot]
Also delete an errant println in InstanceSpec (cherry picked from commit 3462c54c018a52a377f1c89121b6ed99c5b0ae1d) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-03-08Add scanLeftOr and scanRightOr utilies (#2407) (#2437)mergify[bot]
Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 73d3c26029c07c17ce179dfead092eab4fb8ae2c) Co-authored-by: Liu Xiaoyi <circuitcoder0@gmail.com>
2022-03-04Issue errors on out-of-range extracts when width is known (#2428) (#2429)mergify[bot]
* Issue errors on out-of-range extracts when width is known Firrtl will catch this later on, but better to error early if possible. * Test that errors are generated on OOB extracts when width is known (cherry picked from commit 462def429aa87becb544533880a3075a806c53e4) Co-authored-by: Andrew Waterman <andrew@sifive.com>
2022-02-15Make TruthTable accept unknown input width (#2387) (#2417)mergify[bot]
Widths are now padded to the maximum width of the inputs. Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 546b4e13fe90ff09d24b63664c072d46c13c0c38) Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2022-02-11Hierarchy API: make Mems lookupable (#2404) (#2410)mergify[bot]
(cherry picked from commit 2a985ac376698a2e6300fbee13001d82d3e13989) Co-authored-by: Deborah Soung <debs@sifive.com>
2022-02-10Make Tuple2 Lookupable (#2372) (#2406)mergify[bot]
(cherry picked from commit 024847d75079a125e5946e9dcf2ed9c14d2db730) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-02-08Overload getVerilogString to accept arguments (#2401) (#2402)mergify[bot]
(cherry picked from commit b55dc36d4edd1d22db37616235c003c89d68d29b) Co-authored-by: Carlos Eduardo <me@carlosedp.com>
2022-02-03FillInterleaved documentation: swap order of elements in Seq example (#2393) ↵mergify[bot]
(#2395) (cherry picked from commit 055a85298c46c6734880cd828af436adbded1d0a) Co-authored-by: John Ingalls <43973001+ingallsj@users.noreply.github.com>
2022-02-01Improve error reporting (backport #2376) (#2379)mergify[bot]
* Improve error reporting (#2376) * Do not trim stack traces of exceptions with no stack trace This prevents us from accidentally giving stack traces to exceptions that don't have them and giving misleading messages telling users to use --full-stacktrace when it won't actually do anything. Also deprecate ChiselException.chiselStackTrace which is no longer being used anywhere in this codebase. * Add exception class for multiple-errors reported New chisel3.internal.Errors replaces old anonymous class that would show up as chisel3.internal.ErrorLog$$anon$1 in error messages. * Add new option --throw-on-first-error This tells Chisel not to aggregate recoverable errors but instead to throw an exception on the first one. This gives a stack trace for users who need it for debugging. (cherry picked from commit ff2e9c92247b3848659fa09fdd53ddde2120036a) * Waive MiMa false positives The waived change is to a package private constructor. Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2022-02-01Optional clock param for memory ports (#2333) (#2382)mergify[bot]
Warn if clock at memory instantiation differs from clock bound at port creation and port clock is not manually passed Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 465805ec7b2696a985eaa12cf9c6868f11ac2931) Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
2022-02-01Chisel plugin bundle elements handler (#2306) (#2380)mergify[bot]
Adds generation of `Bundle.elements` method to the chores done by the compiler plugin For each `Bundle` find the relevant visible Chisel field members and construct a hard-coded list of the elements and their names implemented as `_elementsImpl` For more details: See plugins/README.md - Should be no change in API - Handles inheritance and mixins - Handles Seq[Data] - Tests in BundleElementSpec Co-authored-by: chick <chick.markley@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 237200a420581519f29149cbae9b3e968c0d01fc) Co-authored-by: Chick Markley <chick@qrhino.com>
2022-01-28Fix Decoder bug for constant 0 and DC (#2363) (#2371)mergify[bot]
* Fix the QMC bug for constant and dontcare output. * Fix the Espresso bug for constant and dontcare output. (cherry picked from commit 46b53320e9ec09fc26d63259f1821f4234640839) Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2022-01-26Expand supported val modifiers for @public (#2365) (#2367)mergify[bot]
(cherry picked from commit 13fb4595b3b21beadaad5ba5c5d131138099d6e1) Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
2022-01-20Fix Compatibility Module io wrapping (#2355) (#2358)mergify[bot]
The new reflection based IO autowrapping for compatibility mode Modules would previously throw a NullPointerExceptions if any hardware were constructed in the Module before "val io" was initialized. The logic is now more robust for this case. Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> (cherry picked from commit 50e6099fbecc041973564514e55f67ffe069459b) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-01-19util: add GrayCode (#2353) (#2354)mergify[bot]
(cherry picked from commit 91d7baa8e7162d736f46b6d4964b09016d2dd172) Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>
2022-01-11Lookupable: add Either version (#2335)Megan Wachs
* Add Lookupable for Either * Lookupable: enhance the @public/@instantiable error message to include traits and Eithers Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-01-10Apply scalafmtJack Koenig
Command: sbt scalafmtAll
2022-01-07Add a Select.ios that works with Definition/Instance, fix isA behavior (#2315)Megan Wachs
* New Feature: Add a Select.ios that works with Definition/Instance * BugFix: isA now truly ignores type parameters
2021-12-17Improve exception message for aliased bundle fields (#2304)Chick Markley
- Shows groups of field names that share a common id (i.e. aliased) - Show, as much as possible, them in the order that fields appear in bundle - Updated BundleSpec's relevant tests Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-12-16BitSet API (#2211)Jiuyang Liu
BitSet is a new experimental parent type for BitPat. It enables more complex operations on BitPats. Co-authored-by: Ocean Shen <shenao6626@gmail.com>
2021-12-15Restore Port to public API and deprecate (#2302)Jack Koenig
Also clean up deprecation warnings for replacement APIs and add clarifying ScalaDoc.
2021-12-15Refactor TruthTable to use Seq (#2217)Jiuyang Liu
This makes the resulting Verilog from decoding a TruthTable deterministic.
2021-12-11reduceTree() now operates on Seq (#2292)Øyvind Harboe
preserves input/output information of the type being reduced. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-12-10Add support for dynamic indexing on Vec identity views (#2298)Jack Koenig
2021-12-09Better MonoConnect error messages (#2248)Aditya Naik
Co-authored-by: Megan Wachs <megan@sifive.com>
2021-12-09catch None.get in BitPat.apply(x: UInt): BitPat (#2276)Jiuyang Liu
Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-12-08Implement DataViews for Seq and Tuple (#2277)Jack Koenig
* DataProducts for Seq and Tuple2-10 in DataProduct companion object * DataViews for Seq and Tuple 2-10 in DataView companion object * HWTuple2-10 Bundles in chisel3.experimental * Implicit conversions from Seq to Vec and Tuple to HWTuple in chisel3.experimental.conversions
2021-12-02Refactor Data.toString (#2197)Aditya Naik
Provides a more intuitive implementation of toString for Data. Utilizes the fact that the compiler plugin provides names earlier than Chisel had in the past so we can accurately guess the name of signals even in the currently elaborating module. Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
2021-12-01Require the chisel3 compiler plugin (#2271)Jack Koenig
As the chisel3 compiler plugin is now required, we can delete unused code for reflective autoclonetype as well as the noPluginTests.
2021-12-01Bugfix - definition name index skipping with D/I (#2249)Aditya Naik
* Bugfix - definition name index skipping with D/I * Add tests to DefinitionSpec * Add failing test * Fix failing test * Update core/src/main/scala/chisel3/internal/Builder.scala Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> * whitespace * revert package private val Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-12-01Remove unused imports for API removed from firrtl (#2269)Jack Koenig
This fixes CI which fails with current firrtl 1.5-SNAPSHOT.
2021-11-29Remove ChiselExecutionOptions and HasChiselExecutionOptions (#2267)Jack Koenig
These were not actually deprecated but any APIs using them were long since deprecated and more recently removed. They also depend on long deprecated APIs in FIRRTL that will soon be removed.
2021-11-29Deprecate chisel3.BackendCompilationUtilities (#2257)Jack Koenig
Also remove as many deprecated APIs as possible by inlining implementations of old deprecated/removed code from firrtl
2021-11-23fix for chipsalliance/firrtl#2421 (#2256)Jiuyang Liu
2021-11-22add documentations to decoder. (#2254)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-17refactor Queue.hasFlush: Boolean to Queue.flush: Option[Bool]. (#2245)Jiuyang Liu
* refactor Queue.hasFlush: Boolean to Queue.flush: Option[Bool]. Using factory Queue(..., hasFlush = true) won't take effects, since in the Queue.apply API, Queue Module is not exposed, thus even user defines hasFlush = true, there is no place for them to give the flush signal. This commit fix this, refactor Queue.hasFlush: Boolean to Queue.flush: Option[Bool], makes user be able to pass the flush signal into Queue Module. * use zip to connect. * refactor docs. Co-authored-by: Megan Wachs <megan@sifive.com>
2021-11-14add tests.Jiuyang Liu
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