| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-07-27 | More compatibility fixes | Jim Lawson | |
| 2016-07-27 | Correct EnqIO/DeqIO Flipped-ness. | Jim Lawson | |
| 2016-07-27 | Additional compatibility code. | Jim Lawson | |
| 2016-07-25 | Enable current (chisel2-style) compatibility mode. | Jim Lawson | |
| 2016-07-25 | Minimize differences with master. | Jim Lawson | |
| Remove .Lit(x) usage. Undo "private" scope change. Change "firing" back to "fire". Add package level NODIR definition. | |||
| 2016-07-25 | Merge branch 'master' into sdtwigg_connectwrap_renamechisel3 | Jim Lawson | |
| 2016-07-25 | Use more idiomatic ScalaTest exception expecting code. | Jim Lawson | |
| 2016-07-25 | catch Bad connection exception | Jim Lawson | |
| 2016-07-21 | Introduce chiselCloneType to distinguish from cloneType. | Jim Lawson | |
| Still fails one test - DirectionSpec in Direction.scala | |||
| 2016-07-21 | Ensure test_wire is sinkable. | Jim Lawson | |
| 2016-07-20 | More literal/width rangling. | Jim Lawson | |
| 2016-07-20 | Distinguish between ?Int.Lit and ?Int.width | Jim Lawson | |
| 2016-07-20 | Generate better names for nodes (#190) | Jack Koenig | |
| For Chisel nodes defined in Module class-level values of type Option or Iterable, we can still use reflection to assign names based on the name of the value. This works for arbitrary nesting of Option and Iterable so long as the innermost type is HasId. Note that this excludes Maps which always have an innermost type of Tuple2[_,_]. | |||
| 2016-07-20 | Compile ok. | Jim Lawson | |
| Need to convert UInt(x) into UInt.Lit(x) or UInt.width(x) | |||
| 2016-07-19 | Fix LitBinding and MultiAssign tests. | Jim Lawson | |
| 2016-07-19 | Incorporate connection logic. | Jim Lawson | |
| Compiles but fails tests. | |||
| 2016-07-19 | Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3 | Jim Lawson | |
| 2016-07-18 | Update Chisel -> chisel3 references. | Jim Lawson | |
| 2016-07-07 | Don't check GCD result before sending it a request | Andrew Waterman | |
| 2016-06-21 | Most of the remaining tests with Module, IO wrapping. | Jim Lawson | |
| 2016-06-21 | New Module, IO, Input/Output wrapping. | Jim Lawson | |
| 2016-06-20 | Rename "package", "import", and explicit references to "chisel3". | Jim Lawson | |
| 2016-06-08 | Move utils into utils | ducky | |
| 2016-06-08 | Rename Chisel -> chisel in tests | ducky | |
| 2016-06-01 | Fix a fairly serious bug whereby Vec's could incorrectly compare as equal (#204) | Wesley W. Terpstra | |
| * chiselTests: include an example of two empty Vectors killing FIRRTL * Aggregate: fix a bug whereby Vec[T] was using equals/hashCode of Seq In Chisel, two vectors are NOT equal just if their contents are equal. For example, two empty vectors should not be considered equal. This patch makes Vec use the HasId._id for equality like other Chisel types. Without this fix, Bundle.namedElts.seen: HashSet[Data]() will eliminate one of the named vectors and emit bad IR. | |||
| 2016-05-20 | Update BackendCompilationUtilities.verilogToCpp to specify top-module | jackkoenig | |
| This prevents Verilator from erroring when it cannot determine the top-module. It also changes the PRINTF_COND guard to correctly use the top-level reset instead of just the top of the Chisel-generated code. | |||
| 2016-05-04 | Multiple assign tester | ducky | |
| Closes #90 | |||
| 2016-05-04 | Rewrite BlackBox IO contract, replace _clock|_reset | Stephen Twigg | |
| The old blackbox behavior still emitted extmodules that have a clk, reset pin and prepended all io's with io_ (ultimately). Most verilog modules do not follow this distinction (or use a slightly different name for clock and so on). Thus, instead BlackBox has been rewritten to not assume a clk or reset pin. Instead, the io Bundle specified is flattened directly into the Module.ports declaration. The tests have been rewritten to compensate for this. Also, added a test that uses the clock pin. As a secondary change, the _clock and _reset module parameters were bad for two reasons. One, they used null as a default, which is a scala best practices violation. Two, they were just not good names. Instead the primary constructor has been rewritten to take an Option[Clock] called override_clock and an Option[Bool] called override_reset, which default to None. (Note how the getOrElse call down below is much more natural now.) However, users may not want to specify the Some(their_clock) so I also added secondary constructors that take parameters named clock and reset and wrap them into Some calls into the primary constructor. This is a better UX because now you can just stipulate clock=blah in instantiation of that module in symmetry with using the clock in the definition of the module by invoking clock. PS: We could also back out of allowing any overrides via the Module constructor and just require the instantiating Module to do submodule.clock := newclock, etc. | |||
| 2016-04-26 | Replace deprecated usage in tests. Issue #149 | Jim Lawson | |
| 2016-04-18 | Add whenever method to TblSpec forall to weed out invalid test values. | Jim Lawson | |
| 2016-04-15 | Test FIRRTL string literals more aggressively | Andrew Waterman | |
| 2016-04-14 | Disallow Counters with negative n | Andrew Waterman | |
| One could make an argument for disallowing n=0, too, but HW generators will benefit from our leniency. Closes #107. Thanks @jackkoenig | |||
| 2016-03-18 | Add test for assertions in modules with pipedlined reset | jackkoenig | |
| 2016-03-18 | Only randomize directory names during testing | jackkoenig | |
| 2016-02-25 | Fixed comment punctuation and made it clearer that using an init() method ↵ | chick | |
| for DeqIO and EnqIO initialization is likely to change. | |||
| 2016-02-24 | Remove the assignment statements in EnqIO and DeqIO Bundle constructors. | chick | |
| Make the corresponding test run faster by giving it a Counter. | |||
| 2016-02-24 | Create a test that breaks because of assignment statements in DeqIO and ↵ | chick | |
| EnqIO bundles | |||
| 2016-02-22 | Fixed improper apostrophe in it's in TesterDriverSpec comments | chick | |
| 2016-02-10 | TesterDriverSpec is simpler and cleaner, extraneous circuit has been removed. | chick | |
| Cleanup comment for finish method in BasicTester, and finishWrapper in TesterDriver. | |||
| 2016-02-10 | The TesterDriverSpec has been made stronger by altering circuit in finish method | chick | |
| 2016-02-10 | Added some comments describing potential use of the finish method hook | chick | |
| clean up the test example | |||
| 2016-02-09 | fixed test for finish method being put in the wrong place | chick | |
| 2016-02-09 | Added support for finish method of BasicTester to be overridden in a ↵ | chick | |
| subclass which allows tester to have clean up and other construction code executed after a user code executed during constructor of that subclass | |||
| 2016-02-08 | Added a simple tests that DeqIO and EnqIO get their directions right and are ↵ | chick | |
| clonable | |||
| 2016-01-30 | Add BlackBox support and test, refactor execute => assertTesterPasses | ducky | |
| 2016-01-28 | Fixed NoneOptionBundleTester to actually instantiate a module without an ↵ | azidar | |
| input port | |||
| 2016-01-28 | Merge branch 'master' into modrefactor | Andrew Waterman | |
| 2016-01-28 | Merge branch 'master' into scalastyle | Andrew Waterman | |
| 2016-01-27 | Add unit test for module deduplication | ducky | |
| 2016-01-16 | Add When test and fix when / elsewhen / otherwise behavior | ducky | |
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index : chiselX | |
| Chisel with SFC compatibility |
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