| Age | Commit message (Collapse) | Author |
|---|
|
|
|
|
|
We can sometimes shim with other workarounds like VecInit or manually
creating a mux
|
|
|
|
|
|
|
|
|
|
This adds an annotator that provides a linkage to the FIRRTL
WiringTransform. This enables synthesizable cross module references
between one source and multiple sinks without changing IO (the
WiringTransform bores through the hierarchy).
Per WiringTransform, this will connect sources to their closest
sinks (as determined by BFS) or fail if ownership is indeterminate.
Make TesterDriver.execute work like Driver.execute:
- annotations are included when running FIRRTL
- custom transforms are run automatically
Also, add a bore method to BoringUtils that allows you to do one source to
multi-sink mapping in a single call. This adds a test that this is doing
the same thing as the equivalent call via disjoint addSink/addSource.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
|
|
Fixes #852
|
|
See https://github.com/freechipsproject/chisel3/issues/867 for future API discussion
|
|
ucb-bar/chisel2-deprecated#734) and test for same.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
This shows errors comparing literals
|
|
|
|
|
|
|
|
|
|
|
|
Provide direct conversion from ChiselIR to FIRRTL.
Provide Driver support for dumping ProtoBuf.
|
|
Resolves #841
|
|
Add chisel3.experimental.IO for programmatic port creation in Raw and
MultiIOModules. suggestName is required to name ports that cannot be
named by reflection. Two ports cannot be given the same name.
|
|
|
|
Fixes #763
Add tests for #763 and #472
This has a few implications
* Constructing a literal no longer increments _T_ suffixes
* Internally, wrapping a literal Bits in Node(...) will work
* Literal Bools work in withReset/withClockAndReset
|
|
* Add test for UIntToOH
* Pad UIntToOH inputs to support oversized output widthds
* Optimize Bits.pad in case of known widths
* Add missing import and fix test in OneHotMuxSpec
|
|
|
|
Resolves #809
|
|
If autoclonetype is unable to determine an outer class, this attempts to insert a null (and give a deprecation warning), preserving old behavior (in some cases) where the new behavior doesn't work.
This doesn't provide full compatibility with old autoclonetype: this does not attempt null insertion in the general first argument (if it's not an outer class reference). Reasoning is that inserting a null for an explicit argument is probably not the right thing to do, and will likely cause a difficult-to-debug NullPointerException (whereas that would be unlikely for an outer class, which is not always referenced in Bundle subclass code).
|
|
SyncReadMem.read with an enable signal currently only works in
compatibility mode, where Wires are implicitly initialized to
DontCare. Fix by explicitly assigning DontCare to the Wire.
This might fix #775.
|
|
Makes Builder.updateBundleStack a bit stricter in deciding how many stack frames to discard by additionally matching against method names and deleting stack frames at or above the frame currently being inserted.
|
|
* Generalize ChiselAnnotation
This allows us to delay creation of Annotations till elaboration is
complete. Also update all annotation-related code.
* Add RunFirrtlTransform
Use a Chisel-specific RunFirrtlTransform API to preserve behavior of old
ChiselAnnotation (now called ChiselLegacyAnnotation)
* Use unique test directories in ChiselRunners.compile
|
|
|
|
|
|
* Better support for autoclonetype of nested Bundles
* Move bundleStack to dynamicContext
* prefer $outer if available, make guesses distinct
* Catch IllegalAccessException in autoclonetype
In strange circumstances this type of exception can occur when accessing $outer
|
|
|
|
|
|
|
|
Also change Data.outerModule to Bundle._outerInst since it is only used
in autoclonetype. _outerInst is also Option[Object] instead of
Option[BaseModule] because the outer object could also be a Bundle.
|
|
|
|
|
|
|
|
|
|
Fixes #746
Also add test for https://github.com/freechipsproject/firrtl/issues/705
|
|
|
|
Prevents DontCare from affecting type inference
Fixes #728
|
