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Shortcut for .asUInt.asBool
Added test to show it works
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decimal
- made .F and .I work for creating fixed point and interval lits from big decimal
- Added NumObject trait which provides new math conversions
- Made a Num object that extends NumObject
- Add this trait to FixedPoint and Interval for backward compatibility
- Removed code that is now in NumObject, keeping things DRY
- Add tests to FixedPointSpec to show lit conversion to double and big decimal
- Add tests to IntervalSpec to show lit conversion to double and big decimal
- Add tests to LiteralExtractorSpec to show general math conversions between BigInts with binary points and double and big decimal
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The BitPat.parse factory though did not remove these from the returned count.
This fixes that adds whitespace and underscores to the unit tests
This is an updated vesion of Chisel PR #1069
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- boundary testing was not taking binary point into account correctly
- add tests to show where things work and where they are supposed to fail
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- getLowestPossibleValue
- getHighestPossibleValue
- getPossibleValues
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This reverts commit 85fe90d5b7ed4e1101b0b3959a1d362eb93915ac.
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* Use macro to materialize CompileOptions in Chisel._
This switches from using an implicit val that required awkward
suppression (as illustrated in CompileOptionsSpec) to allowing
overriding in the same way as done in "import chisel3._" via the
creation of an implicit val in lexical scope.
* Deprecate Chisel.defaultCompileOptions
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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Accomplished by changing the code gen for casting literals to
aggregates. Rather than connecting the literal to a wire that is then
bit selected from, just bit select from the literal which saves the
creation of an intermediate wire and matches FIRRTL's semantics for
legal async reset initial values.
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Plan to be released with 3.3.
Breaks experimental Range API.
Adds new Interval type and associated support.
This commit adds the following:
- Renamed Range to IntervalRange to avoid name collision with scala Range
- Changed RangeTransform macro to Return an IntervalRange
- Improved error messages on missing comma or decimal
- Added notational support for binary point
- Some formatting cleanup also
- SIntFactory
- Change to use IntervalRange API
- UIntFactory
- UInt from range has custom width computation
- It does not need to deal with lowerbound extending bit requirements
- Code to handle special case of range"[0,0]" to have a width of 1
- IR.scala
- Removed Bound and other constraint code that was duplicating firrtl stuff
- Added new RangeType
- Added IntervalRange class and object
- RangeSpec
- modified just a bit to handle notational differences
- previous range interpolator returned tuple now returns IntervalRange
- Add IntervalType to emitter
- Added IntervalSpec with many tests
- Added ScalaIntervalSimulatorSpec which tests golden model for Interval
- Added ScalaIntervalSimulator which is a golden model for Interval
- This gold may not have been polished to a high sheen
- Add IntervalLit cases to Converter
- Add Interval PrimOps to IR
- asInterval, wrap, squz, clip, setp, decp, incp
- Add IntervalLit class to IR
- Add Interval to MonoConnect
- Add Interval Type to Bits (in experimental package)
- add conversions to Interval from other types
- Add Interval clone stuff to Data
- Add Literal creation helpers to chisel3 package
- these may move to experimental if I can figure that out
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Dynamically indexing a Vec of Flipped bidirectional Bundles would get
the wrong directions on the elements of the Bundles
Fixes #1192
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Add a tree reduce function to Vec
* Change function names of reduce operation function in Vec
* Change reference to single layer operation in Vec.reduce
* Commint name change for pair macro
* Remove pair, call not necessary and can just be used from grouped(2) and map
* Changed to reduceTree, added default identity function for single reduce.
* Change style of Vec.reduceTree and tests to chisel3 and canonical Scala style
* Cleanup Vec initialization, implicitCompileOptions
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* Move dontTouch out of experimental package.
* Move RawModule, MultiIOModule out of experimental.
* Respond to comments - Move LagacyModule from experimental to internal.
*NOTE*: At some point, these module definitions (especially those in separate packages) should be moved to individual files at the appropriate location in the source tree. The current organization is purely to support comparison with prior versions.
* Fix up a few more imports.
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Use FIRRTL stage-style testing to check stdout printing without and
with --full-stacktrace.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds methods for examining stdout/stderr and exit codes inside of
a Scala program. This are pulled directly from firrtlTests, but we
aren't currently publishing those anywhere that we can get at them.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Adds new AsyncReset and "abstract" Reset types. Reset is inferred
in FIRRTL to be either AsyncReset or Bool. The "reset type" of a
register is set by the type of its reset signal:
val asyncReset: AsyncReset = IO(Input(AsyncReset()))
val syncReset: Bool = IO(Input(Bool()))
val abstractReset: Reset = IO(Input(Reset()))
val asyncReg = withReset(asyncReset) { RegInit(0.U) }
val syncReg = withReset(syncReset) { RegInit(0.U) }
val inferredReg = withReset(abstractReset) { RegInit(0.U) }
AsyncReset can be cast to and from Bool. Whereas synchronous reset is
equivalent to a mux in front of a flip-flop and thus can be driven by
logic, asynchronous reset requires that the reset value is a constant.
This is checked in FIRRTL.
Inference of the concrete type of a Reset occurs based on the type the
Reset's drivers. This inference is very simple, it is simple forward propagation
of the type, but it allows for writing blocks and modules that are agnostic
to the reset type. In particular, the implicit `reset` value in MultiIOModule
and thus Module is now concretely an instance of Reset and thus will be
inferred in FIRRTL.
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Added Aspects to Chisel, enabling a mechanism for dependency injection to hardware modules.
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Adds a check that a Vec being indexed by a UInt is, in fact, a
hardware type. This includes a test for this.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Short-term patch to enable this useful behavior. In the future, we may want to rearchitect the type system and/or rethink the more edge-case connect behavior.
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* Add width utility functions to avoid incorrect usage of bare log2Ceil().
* Respond to comments:
Remove apply(Data) method.
Change name(s) to signedBitLength, unsignedBitLength.
* Respond to comments - don't be lazy.
Independently calculate the bit length to verify correct operation.
* Respond to comments - return in.bitLength - 0 (not 1) for 0
* Respond to comments - update wdith for signed 0; add explicit tests.
* Add comment expressing zero width wire assumption.
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function. This also fixes prior issue where ChiselEnums would not
compile when @chiselName was applied to a module containing a ChiselEnum
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This converts the original chisel3.Driver to use
chisel3.stage.ChiselStage. This is implemented in the following way:
1. ExecutionOptions are converted to an AnnotationSeq
2. The AnnotationSeq is preprocessed using phases contained in the
Chisel DriverCompatibility objects. One of these *disables* the
execution of FirrtlStage by ChiselStage.
3. ChiselStage runs on the preprocessed AnnotationSeq
4. The input ExecutionOptionsManager is mutated based on the output
of ChiselStage.
5. The FIRRTL stage is re-enabled if it's supposed to run and
selected FIRRTL DriverCompatibility phases run.
6. FirrtlStage runs
7. The output AnnotationSeq is "viewed" as a ChiselExecutionResult
This modifies the original DriverSpec to make it more verbose with the
addition of info statements. The functionality of the DriverSpec is
unmodified.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds an Emitter Phase that writes a ChiselCircuitAnnotation to
a file if a ChiselOutputFileAnnotation is present.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This coalesces three distinct operations into one Convert Phase:
1. Chisel Circuit to FIRRTL Circuit (CHIRRTL) conversion
2. Conversion of Chisel Annotations to FIRRTL Annotations
3. Generation of RunFirrtlTransformAnnotations
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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