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2022-02-15Make TruthTable accept unknown input width (#2387) (#2417)mergify[bot]
Widths are now padded to the maximum width of the inputs. Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 546b4e13fe90ff09d24b63664c072d46c13c0c38) Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2022-01-10Apply scalafmtJack Koenig
Command: sbt scalafmtAll
2021-12-16BitSet API (#2211)Jiuyang Liu
BitSet is a new experimental parent type for BitPat. It enables more complex operations on BitPats. Co-authored-by: Ocean Shen <shenao6626@gmail.com>
2021-12-15Refactor TruthTable to use Seq (#2217)Jiuyang Liu
This makes the resulting Verilog from decoding a TruthTable deterministic.
2021-12-09catch None.get in BitPat.apply(x: UInt): BitPat (#2276)Jiuyang Liu
Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-09-06Test case reworkBoyang Han
2021-09-06Add a test case to demonstrate the bug found in #2112Boyang Han
2021-08-26add new APIs to BitPat (#2076)Jiuyang Liu
* add Y and N to BitPat. * add ## for BitPat. * add rawString API. * use rawString in decoder * add select and slice to BitPat.
2021-08-25replace custom model checker with chiseltest formal verify command (#2075)Kevin Laeufer
* replace custom model checker with chiseltest formal verify command * integration-tests can make use of chiseltest This is a compromise solution to avoid issues with binary compatibility breaking changes in chisel3. * ci: move integration tests into separate job * run integration tests only for one scala version * ci: install espresso for integration tests * Update build.sbt Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
2021-07-14Fix Cat rename signal (#2011)Leway Colin
Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-07-14Espresso Decoder (#1964)Jiuyang Liu
Co-authored-by: Haoran Yuan <sinofp@tuta.io> Co-authored-by: Boyang Han <yqszxx@gmail.com>
2021-06-30Add 7 segment display decoder test caseBoyang Han
2021-06-16implement test for qmcJiuyang Liu
2021-06-16Add test cases.Jiuyang Liu
2021-06-16switch to EndToEndSMTBaseSpecJiuyang Liu
2021-06-16Add minimized form of test casesBoyang Han
2021-06-16use z3 formal check minimized circuit and reference model.Jiuyang Liu
2021-06-16test decode cache.Jiuyang Liu
2021-06-16TruthTable can merge same inputs now.Jiuyang Liu
2021-06-16implement TruthTable to represent a decode table.Jiuyang Liu
2021-05-25throw exception if BitPat width is 0 (#1920)Jiuyang Liu
* spot a bug when BitPat width is 0 * fix #1919 Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-20Implement PLA (#1912)Jiuyang Liu
* implement pla * implement test for pla * implement inverter matrix of PLA generator * fix for review. Co-authored-by: Boyang Han <yqszxx@gmail.com>
2021-03-18Add toString method to BitPat (#1819)Boyang Han
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-01-21Rename MultiIOModule to ModuleJack Koenig
2020-10-19Enable Cat of Zero Element Vec (#1623)Schuyler Eldridge
* Return 0.U for asUInt of a zero-element Seq Add a condition to SeqUtils.asUInt to have it return an unspecified width 0.U when applied to an empty sequence. This enables the ability to do a Cat of a zero-element sequence. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Test elaboration of Cat on zero-element Seq Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
Change source and other relevant files to use SPDX license LICENSE file moved from src/ to ./ Changed license file to refer to this per recommendation using_spdx_license_list_short_identifiers WARNING: Tests fail with as of yet undiagnosed error ``` [error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15 [error] Failed tests: [error] chiselTests.QueueSpec [error] examples.VendingMachineGeneratorSpec [error] chiselTests.HarnessSpec [error] chiselTests.ConnectSpec [error] chiselTests.aop.SelectSpec [error] chiselTests.PopCountSpec [error] chiselTests.CloneModuleSpec [error] (Test / test) sbt.TestsFailedException: Tests unsuccessful [error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM sbt:chisel3> ```
2020-07-21Delete outdated scalastyle configuration comments from sourceAlbert Magyar
2020-06-29- A few final fixes after the rebasechick
2020-06-22Use ChiselStage in TestsSchuyler Eldridge
This migrates the tests to Chisel 3.4/FIRRTL 1.4. This primarily involves removing usages of deprecated methods including: - Remove usages of Driver - Use ChiselStage methods instead of BackendCompilationUtilities methods - Use Dependency API for custom transforms - Use extractCause to unpack StackError Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-16Move Deprecated LFSR16 to CompatibilitySchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-09PRNG state UInt->Vec[Bool], make async reset safeSchuyler Eldridge
Changes the internal state of PRNG to use Vec[Bool] instead of UInt. This fixes an @aswaterman identified future problem with asynchronous reset. A register with an asynchronous reset can only be reset to a literal. Previously, an LFSR would store state as a UInt. If it was not parameterized with a seed it should have its least significant bit reset to something to avoid locking up. It's ideal to not reset the full UInt (better test coverage, decreased reset fanout). However, it's difficult to only reset one bit of a UInt. Conversely, it's trivial to reset one bit of a Vec[Bool]. This also moves PRNG/LFSR closer to a canonical representation of their internal state, i.e., it's natural to think of generalizing Vec[Bool] to arbitrary finite fields (Vec[A <: Field]) whereas UInt is tightly coupled to GF2. Minor updates: - Updates/fixes to some scaladoc - Add assertion to period test to make sure LFSR is changing Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-09Add Lfsr testsSchuyler Eldridge
Add LFSR tests using LFSR16 testing infrastructure. This also adds tests that are the same as the examples shown for LFSR scaladoc. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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